EPM3512AFC256-2 vs EPM3512AFC256-19 Perbandingan

Perbandingan bersamaan detil EPM3512AFC256-2 dari Altera dan EPM3512AFC256-19 dari Altera. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.

Perbandingan Spesifikasi

Parameter Umum EPM3512AFC256-2 EPM3512AFC256-19
Merek Altera Altera
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Obsolete NRND
Family MAX 3000A MAX 3000A
Macrocells 512 512
Logic Array Blocks (LABs) 16 16
Maximum User I/O Pins 212 —
Propagation Delay (tPD, -2 grade) [DATA_NEEDED: tPD ns] —
Maximum Operating Frequency [DATA_NEEDED: fMAX MHz] 80 MHz
Core Supply Voltage 3.3 V —
I/O Output Drive Voltage 2.5 V or 3.3 V (MultiVolt) —
Input Tolerance 2.5 V, 3.3 V, 5.0 V tolerant —
Paket BGA-256 (FineLine BGA) 256-ball FineLine BGA (FC)
Ball Pitch 1.0 mm —
Programming Interface JTAG (IEEE Std 1149.1) / ByteBlaster JTAG (IEEE 1149.1) / ISP (IEEE 1532)
Process Technology 0.30 um CMOS EEPROM 0.30 µm CMOS EEPROM
Suhu Kerja 0C to +70C (commercial) -40C to +85C (industrial)
Status RoHS [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS status]
Speed Grade -2 -19
Device Type — CPLD (Complex Programmable Logic Device)
Usable Gates — 10000
Pin-to-Pin Delay (tPD) — 7.5 ns
User I/O Pins — 208
Supply Voltage VCCINT — 3.3 V
I/O Supply Voltage VCCIO — 2.5 V or 3.3 V (5.0 V tolerant inputs)
Non-volatile Configuration — Yes (EEPROM-based)
Tipe Mounting — Surface Mount

Spek dan Sumber

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