EPM5192JC2 vs EPM5192JC Perbandingan
Perbandingan bersamaan detil EPM5192JC2 dari Intel dan EPM5192JC dari Intel. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.
Perbandingan Spesifikasi
| Parameter Umum | EPM5192JC2 | EPM5192JC |
|---|---|---|
| Merek | Intel | Intel |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Obsolete | Obsolete |
| Family | MAX 5000 | — |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 192 | 192 |
| Logic Array Blocks (LABs) | 12 | 12 |
| Usable Gates (equivalent) | 6000 | — |
| Maximum User I/O | 64 | — |
| Dedicated Inputs | 7 | — |
| External Clock Inputs | 1 (with shared input/clock capability) | — |
| Frekuensi Bawah Maximum | 50 MHz | — |
| Propagation Delay (tPD) | 45 ns (speed grade -2) | — |
| Process Technology | CMOS, UV-erasable | CMOS EPROM (UV-erasable) |
| Interconnect | Programmable Interconnect Array (PIA) | — |
| Paket | PLCC-68 (JC) | 68-pin PLCC (JC) windowed ceramic |
| Tipe Mounting | Surface Mount (socketable PLCC) | Surface Mount |
| Programming | Altera Master Programmer / ByteBlaster via JTAG-style interface | — |
| Product Type | — | CPLD (Complex Programmable Logic Device) |
| Series | — | EPM5192 (Classic / MAX-class) |
| Interconnect Architecture | — | Programmable Interconnect Array (PIA) |
| Programming Method | — | UV-erase + EPROM programmer |
| Non-Volatile Configuration | — | Yes (EPROM cell array) |
| Logic Family | — | Classic CPLD (EPM5xxx series) |
| Suhu Kerja | — | [DATA_NEEDED: commercial / industrial / military grade] |
| Tegangan Pemuat | — | [DATA_NEEDED: VCC nominal] |
| Propagation Delay | — | [DATA_NEEDED: tpd spec by speed grade] |
| Status RoHS | — | [DATA_NEEDED: original Altera marking not RoHS] |