EPM5192JC2 vs EPM5192JC 比較
詳細並排比較 EPM5192JC2 由 Intel 與 EPM5192JC 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM5192JC2 | EPM5192JC |
|---|---|---|
| 品牌 | Intel | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | MAX 5000 | — |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 192 | 192 |
| Logic Array Blocks (LABs) | 12 | 12 |
| Usable Gates (equivalent) | 6000 | — |
| Maximum User I/O | 64 | — |
| Dedicated Inputs | 7 | — |
| External Clock Inputs | 1 (with shared input/clock capability) | — |
| 最大時脈頻率 | 50 MHz | — |
| Propagation Delay (tPD) | 45 ns (speed grade -2) | — |
| Process Technology | CMOS, UV-erasable | CMOS EPROM (UV-erasable) |
| Interconnect | Programmable Interconnect Array (PIA) | — |
| 封裝 | PLCC-68 (JC) | 68-pin PLCC (JC) windowed ceramic |
| 安裝類型 | Surface Mount (socketable PLCC) | Surface Mount |
| Programming | Altera Master Programmer / ByteBlaster via JTAG-style interface | — |
| Product Type | — | CPLD (Complex Programmable Logic Device) |
| Series | — | EPM5192 (Classic / MAX-class) |
| Interconnect Architecture | — | Programmable Interconnect Array (PIA) |
| Programming Method | — | UV-erase + EPROM programmer |
| Non-Volatile Configuration | — | Yes (EPROM cell array) |
| Logic Family | — | Classic CPLD (EPM5xxx series) |
| 工作溫度 | — | [DATA_NEEDED: commercial / industrial / military grade] |
| 供應電壓 | — | [DATA_NEEDED: VCC nominal] |
| Propagation Delay | — | [DATA_NEEDED: tpd spec by speed grade] |
| RoHS 狀態 | — | [DATA_NEEDED: original Altera marking not RoHS] |