EPM7096LC84-15 vs EPM7096LC84-10 Perbandingan

Perbandingan bersamaan detil EPM7096LC84-15 dari Altera dan EPM7096LC84-10 dari Intel. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.

Perbandingan Spesifikasi

Parameter Umum EPM7096LC84-15 EPM7096LC84-10
Merek Altera Intel
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Obsolete NRND
Family MAX 7000 MAX 7000
Series MAX 7000 (second-generation MAX architecture) —
Macro Cells 96 —
Logic Array Blocks (LABs) 4 4
Usable Gates 1,800 —
Pin-to-Pin Propagation Delay (tPD) 15 ns —
Maximum Operating Frequency 76.9 MHz —
User I/O Pins 68 (36 per LAB, [DATA_NEEDED: exact LAB-level split]) —
Supply Voltage (VCC) 4.75 V to 5.25 V 5.0 V nominal (4.75 V - 5.25 V)
Programmable Type EE PLD (in-system programmable via JTAG) —
Programming Interface IEEE Std. 1149.1 JTAG —
Suhu Kerja 0C to +70C (commercial) —
Paket / Case 84-PLCC (J-Lead) —
Supplier Device Package 84-PLCC (29.31 x 29.31 mm) —
Tipe Mounting Surface Mount Surface Mount (PLCC socket or SMT)
Data Retention [DATA_NEEDED: data retention years] —
Erase/Program Endurance [DATA_NEEDED: erase/program cycle count] —
Status RoHS [DATA_NEEDED: RoHS compliance status] [DATA_NEEDED: RoHS status]
Device Type — CPLD (Complex Programmable Logic Device)
Macrocells — 96
Maximum User I/O Pins — 36
Propagation Delay (tPD) — 10 ns (-10 speed grade)
Paket — 84-PLCC (J-Lead)
Process Technology — EEPROM-based, 5.0 V low-power CMOS (L)
In-System Programmability — Yes, via IEEE 1149.1 JTAG
MultiVolt I/O — 2.5 V / 3.3 V / 5.0 V mixed-voltage interface
Rentang Suhu Kerja — 0C to +70C (Commercial, 'C')
Configuration Memory — Non-volatile EEPROM (instant-on)
Programmable Interconnect — PIA (Programmable Interconnect Array)

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