EPM9320GC280-15 vs EPM9560GC280-15N Perbandingan

Perbandingan bersamaan detil EPM9320GC280-15 dari Altera dan EPM9560GC280-15N dari Intel. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.

Perbandingan Spesifikasi

Parameter Umum EPM9320GC280-15 EPM9560GC280-15N
Merek Altera Intel
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Obsolete NRND
Family MAX 9000 (EPM9320) —
Device Type CPLD - Complex Programmable Logic Device —
Architecture CMOS EEPROM-based, Multiple Array MatriX (MAX) Multiple Array MatriX (MAX) 3rd generation
Usable Gates 6,000 12,000 (typical)
Macrocells 320 —
Logic Array Blocks (LABs) 20 (16 macrocells per LAB) —
Pin-to-Pin Propagation Delay 15 ns —
Maximum Internal Frequency 117.6 MHz —
Maximum User I/O Pins 164 —
Supply Voltage (VCC) 4.75 V to 5.25 V —
I/O Voltage Levels 3.3 V or 5 V (configurable) —
Programmability 5.0-V in-system programmable (ISP) via IEEE 1149.1 JTAG —
Paket 280-pin Ceramic Pin Grid Array (CPGA-280) CPGA-280 (Ceramic Pin Grid Array, 280 pins)
Tipe Mounting Through-hole (PGA socket) —
Suhu Kerja 0 C to +70 C (commercial) —
Level MSL 3 (168 hours) —
Status RoHS ROHS3 compliant (per fpgalink listing) —
Technology Node CMOS EEPROM, third-generation MAX —
Device Family — MAX 9000
Product Type — EE PLD / CPLD
Macrocell Count — 560
Propagation Delay (tPD) — 16.6 ns
Frekuensi Bawah Maximum — 117.6 MHz
Supply Voltage (VCCINT/VCCIO) — 5.0 V
Maximum Supply Voltage — 5.25 V
Logic Technology — CMOS EEPROM
In-System Programmability — Yes (5.0-V ISP via JTAG)
Boundary-Scan (JTAG) — IEEE Std. 1149.1 compliant
Package Code — PGA / CPGA280
Terminal Form — PIN/PEG
Operating Temperature Grade — Commercial

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