EPM9320RI208-20N vs EPM9320RI208-10N Perbandingan

Perbandingan bersamaan detil EPM9320RI208-20N dari Altera dan EPM9320RI208-10N dari Altera. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.

Perbandingan Spesifikasi

Parameter Umum EPM9320RI208-20N EPM9320RI208-10N
Merek Altera Altera
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup NRND Aktif
Device Family MAX 9000 (EPM9320) —
Logic Type EEPROM-based Complex Programmable Logic Device (CPLD) —
Macrocells 320 —
Flip-Flops 484 —
Propagation Delay (tPD) 20 ns —
Supply Voltage (VCC) 5.0 V —
I/O Voltage Tolerance 3.3 V or 5 V configurable —
Paket 208-pin PQFP (Plastic Quad Flat Pack) 208-pin RQFP (PowerQuad II)
Package Lead Pitch 0.500 mm —
Number of Terminals 208 —
Rentang Suhu Kerja -40C to +85C (Industrial) -40C to +85C (industrial)
In-System Programmability Yes, 5.0 V ISP via JTAG Yes (JTAG/ISP)
JTAG Interface IEEE Std. 1149.1 compliant —
Configuration Memory EEPROM (non-volatile) EEPROM (non-volatile)
Dedicated Input Pins 4 (low-skew global distribution) —
Minimum DC Input on I/O Pins -0.5 V —
Minimum DC Input on Dedicated Inputs -0.3 V —
Input Undershoot/ Overshoot -2.0 V / 7.0 V for <20 ns (no-load) —
Tipe Mounting Surface Mount Surface Mount
Status RoHS [DATA_NEEDED: RoHS status] Compliant (N suffix = lead-free)
Family — MAX 9000
Device Type — Complex Programmable Logic Device (CPLD)
Usable Gates — 6,000
Macro Cells — 320
Logic Array Blocks (LABs) — 20
Pin-to-Pin Propagation Delay (tPD) — 10 ns
Maximum System Clock Frequency — 100 MHz
Tegangan Pemuat — 5 V
I/O Voltage — 5 V
User I/O Pins — 160
Lead Finish — Lead-free (matte tin)
Level MSL — [DATA_NEEDED: MSL level]

Spek dan Sumber

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