EPM9480RC240-20 vs EPM9560R1208-20 Perbandingan

Perbandingan bersamaan detil EPM9480RC240-20 dari Altera dan EPM9560R1208-20 dari Altera. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.

Perbandingan Spesifikasi

Parameter Umum EPM9480RC240-20 EPM9560R1208-20
Merek Altera Altera
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup NRND Obsolete
Family MAX 9000 MAX 9000
Device Type CPLD (Complex Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Macrocells 480 560
Usable Gates 10,000 6,000
Logic Elements 30 —
User I/O Pins 175 —
Number of Terminals 240 —
Paket 240-RQFP (32x32 mm, FQFP, Gull Wing) R-1208 (BGA-style fine-pitch)
Maximum Propagation Delay (tpd) 20 ns —
Maximum Internal Frequency (fMAX, related -C variant) 100 MHz —
Programmable Flip-Flops (family) 676 —
Internal Supply Voltage 4.75 V to 5.25 V —
I/O Signaling Levels 3.3 V or 5 V (configurable) —
Process Technology CMOS EEPROM CMOS EEPROM, third-generation MAX architecture
Programming Interface In-System Programmable (ISP) via IEEE 1149.1 JTAG —
Operating Temperature Grade Commercial —
Terminal Form Gull Wing —
Status RoHS [DATA_NEEDED: RoHS status] [DATA_NEEDED: confirm via current distributor data]
Logic Array Blocks — 52 (typical for 560 macrocells)
Maximum User I/O — 212
Propagation Delay (tPD) — 20 ns
Maximum Frequency (fMAX) — 125 MHz
Supply Voltage (VCCINT/VCCIO) — 5.0 V
Technology — CMOS EEPROM
In-System Programmability — Yes (IEEE 1149.1 JTAG)
Suhu Kerja — 0C to +70C (commercial)
Tipe Mounting — Surface Mount
Architecture — Multiple Array MatriX (MAX) with Logic Array Blocks (LABs) and Programmable Interconnect Array (PIA)
Boundary-Scan Test — JTAG IEEE Std. 1149.1
Configuration Memory — On-chip EEPROM (non-volatile)

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