EPM9560R1208-20 vs EPM9560ARC208-10 Perbandingan

Perbandingan bersamaan detil EPM9560R1208-20 dari Altera dan EPM9560ARC208-10 dari Intel. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.

Perbandingan Spesifikasi

Parameter Umum EPM9560R1208-20 EPM9560ARC208-10
Merek Altera Intel
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Obsolete Obsolete
Family MAX 9000 —
Device Type CPLD (Complex Programmable Logic Device) —
Usable Gates 6,000 12,000 gates
Macrocells 560 560 macrocells
Logic Array Blocks 52 (typical for 560 macrocells) 35 LABs
Maximum User I/O 212 —
Propagation Delay (tPD) 20 ns 10 ns (speed grade -10)
Maximum Frequency (fMAX) 125 MHz —
Supply Voltage (VCCINT/VCCIO) 5.0 V —
Technology CMOS EEPROM —
In-System Programmability Yes (IEEE 1149.1 JTAG) —
Suhu Kerja 0C to +70C (commercial) 0 C to +70 C (commercial)
Paket R-1208 (BGA-style fine-pitch) 208-pin RQFP (PowerQuad Flat Pack) with exposed pad
Tipe Mounting Surface Mount Surface Mount
Process Technology CMOS EEPROM, third-generation MAX architecture —
Architecture Multiple Array MatriX (MAX) with Logic Array Blocks (LABs) and Programmable Interconnect Array (PIA) —
Boundary-Scan Test JTAG IEEE Std. 1149.1 —
Configuration Memory On-chip EEPROM (non-volatile) —
Status RoHS [DATA_NEEDED: confirm via current distributor data] [DATA_NEEDED: RoHS status]
Device Family — MAX 9000A (Multiple Array MatriX)
Programmable Logic Type — CPLD (Complex Programmable Logic Device)
User I/O Pins — 153 I/O
Internal Frequency — 144.9 MHz
Tegangan Pemuat — 5.0 V
Logic Family — CMOS
Configuration Technology — EEPROM (non-volatile, in-system programmable)
JTAG Interface — IEEE 1149.1 boundary-scan (ISP)
Jumlah Pin — 208 pins

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