EPM9560RC208-15 vs EPM9560ARC208-10 Perbandingan

Perbandingan bersamaan detil EPM9560RC208-15 dari Altera dan EPM9560ARC208-10 dari Intel. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.

Perbandingan Spesifikasi

Parameter Umum EPM9560RC208-15 EPM9560ARC208-10
Merek Altera Intel
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Obsolete Obsolete
Family MAX 9000 —
Device Type EEPROM-based Complex Programmable Logic Device (CPLD) —
Usable Gates 12,000 gates 12,000 gates
Macro Cells 560 macro cells —
Pin-to-Pin Delay 15 ns —
Counter Speed 117.6 MHz —
Tegangan Pemuat 5.0 V 5.0 V
Configuration Technology EEPROM (non-volatile) EEPROM (non-volatile, in-system programmable)
In-System Programmability Yes, via IEEE Std. 1149.1 JTAG —
Paket 208-pin RQFP (Power Quad Flat Pack) 208-pin RQFP (PowerQuad Flat Pack) with exposed pad
Tipe Mounting Surface Mount Surface Mount
Suhu Kerja [DATA_NEEDED: operating temperature range] 0 C to +70 C (commercial)
Number of I/O Pins [DATA_NEEDED: number of I/O pins] —
Logic Array Blocks [DATA_NEEDED: number of logic array blocks] 35 LABs
Status RoHS [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS status]
Speed Grade -15 (15 ns pin-to-pin) —
Architecture Third-generation Multiple Array MatriX (MAX) —
Device Family — MAX 9000A (Multiple Array MatriX)
Programmable Logic Type — CPLD (Complex Programmable Logic Device)
Macrocells — 560 macrocells
User I/O Pins — 153 I/O
Propagation Delay (tPD) — 10 ns (speed grade -10)
Internal Frequency — 144.9 MHz
Logic Family — CMOS
JTAG Interface — IEEE 1149.1 boundary-scan (ISP)
Jumlah Pin — 208 pins

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