EPM9560RC208-4 vs EPM9560RC208-15 Perbandingan

Perbandingan bersamaan detil EPM9560RC208-4 dari Altera dan EPM9560RC208-15 dari Altera. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.

Perbandingan Spesifikasi

Parameter Umum EPM9560RC208-4 EPM9560RC208-15
Merek Altera Altera
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Obsolete Obsolete
Family MAX 9000 MAX 9000
Device EPM9560 —
Macrocells 560 —
Usable Gates 12,000 12,000 gates
Logic Array Blocks (LABs) 16 —
Maximum Operating Frequency 118.3 MHz —
Pin-to-Pin Delay (tPD) 4 ns —
Speed Grade -4 -15 (15 ns pin-to-pin)
Supply Voltage (VCC) 5 V —
Paket 208-pin RQFP (Power Quad Flat Pack) 208-pin RQFP (Power Quad Flat Pack)
User I/O Pins 96 (approx., 208-pin RQFP) —
Dedicated Inputs 16 —
Programming Interface IEEE 1149.1 JTAG (ISP) —
Configuration Memory EEPROM (non-volatile) —
MultiVolt I/O 5.0 V / 3.3 V / 2.5 V —
Suhu Kerja 0C to +70C (commercial) [DATA_NEEDED: operating temperature range]
Status RoHS [DATA_NEEDED: RoHS compliance status] [DATA_NEEDED: RoHS status]
Device Type — EEPROM-based Complex Programmable Logic Device (CPLD)
Macro Cells — 560 macro cells
Pin-to-Pin Delay — 15 ns
Counter Speed — 117.6 MHz
Tegangan Pemuat — 5.0 V
Configuration Technology — EEPROM (non-volatile)
In-System Programmability — Yes, via IEEE Std. 1149.1 JTAG
Tipe Mounting — Surface Mount
Number of I/O Pins — [DATA_NEEDED: number of I/O pins]
Logic Array Blocks — [DATA_NEEDED: number of logic array blocks]
Architecture — Third-generation Multiple Array MatriX (MAX)

Spek dan Sumber

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