EPM9560RC208-4 vs EPM9560RC208-15 比較
詳細並排比較 EPM9560RC208-4 由 Altera 與 EPM9560RC208-15 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM9560RC208-4 | EPM9560RC208-15 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | MAX 9000 | MAX 9000 |
| Device | EPM9560 | — |
| Macrocells | 560 | — |
| Usable Gates | 12,000 | 12,000 gates |
| Logic Array Blocks (LABs) | 16 | — |
| Maximum Operating Frequency | 118.3 MHz | — |
| Pin-to-Pin Delay (tPD) | 4 ns | — |
| Speed Grade | -4 | -15 (15 ns pin-to-pin) |
| Supply Voltage (VCC) | 5 V | — |
| 封裝 | 208-pin RQFP (Power Quad Flat Pack) | 208-pin RQFP (Power Quad Flat Pack) |
| User I/O Pins | 96 (approx., 208-pin RQFP) | — |
| Dedicated Inputs | 16 | — |
| Programming Interface | IEEE 1149.1 JTAG (ISP) | — |
| Configuration Memory | EEPROM (non-volatile) | — |
| MultiVolt I/O | 5.0 V / 3.3 V / 2.5 V | — |
| 工作溫度 | 0C to +70C (commercial) | [DATA_NEEDED: operating temperature range] |
| RoHS 狀態 | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS status] |
| Device Type | — | EEPROM-based Complex Programmable Logic Device (CPLD) |
| Macro Cells | — | 560 macro cells |
| Pin-to-Pin Delay | — | 15 ns |
| Counter Speed | — | 117.6 MHz |
| 供應電壓 | — | 5.0 V |
| Configuration Technology | — | EEPROM (non-volatile) |
| In-System Programmability | — | Yes, via IEEE Std. 1149.1 JTAG |
| 安裝類型 | — | Surface Mount |
| Number of I/O Pins | — | [DATA_NEEDED: number of I/O pins] |
| Logic Array Blocks | — | [DATA_NEEDED: number of logic array blocks] |
| Architecture | — | Third-generation Multiple Array MatriX (MAX) |