EPM9560RC240-3 vs EPM9560RC240-1O Perbandingan

Perbandingan bersamaan detil EPM9560RC240-3 dari Altera dan EPM9560RC240-1O dari Intel. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.

Perbandingan Spesifikasi

Parameter Umum EPM9560RC240-3 EPM9560RC240-1O
Merek Altera Intel
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Obsolete Waktu Pembelian Terakhir
Device Type Complex Programmable Logic Device (CPLD) —
Family MAX 9000 MAX 9000
Macrocells 560 560
Usable Gates 12000 12,000
Logic Array Blocks (LABs) 20 35
Pin-to-Pin Propagation Delay 3 ns (speed grade -3) —
Maximum Operating Frequency [DATA_NEEDED: fMAX] —
Supply Voltage (VCCINT) 5 V —
Supply Voltage (VCCIO) 5 V —
User I/O Pins 192 —
Paket 240-pin RQFP (PowerQuad II) RQFP-240 (240-pin Reduced-height QFP)
Tipe Mounting Surface Mount Surface Mount
Configuration Memory EEPROM (non-volatile) —
Rentang Suhu Kerja 0C to +70C (commercial) —
Status RoHS [DATA_NEEDED: RoHS] Compliant (per Altera/Intel product page)
Lead Finish [DATA_NEEDED: lead finish] —
Level MSL [DATA_NEEDED: MSL] —
JTAG Support [DATA_NEEDED: JTAG] —
Maximum User I/O Pins — 216
Propagation Delay (tPD) — 12 ns (typ, -1 speed grade)
Global Setup Time (tFSU) — 3.0 ns
Clock-to-Output (tFCO) — 4.8 ns
Maximum Internal Frequency (fCNT) — 145 MHz
Supply Voltage (VCC) — 5.0 V
Operating Temperature (Grade) — -40C to +85C (industrial, "-1O" suffix)
Process Technology — CMOS EEPROM, 0.65 um
Programming — In-system programmable via IEEE 1149.1 JTAG
Architecture — Multiple Array MatriX (MAX), third generation
Lead-Free — Yes

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