EPM9560RC240-3 vs EPM9560RC240-1O Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM9560RC240-3 sa pamamagitan ng Altera at EPM9560RC240-1O sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
EPM9560RC240-1O - MAX 9000 CPLD, 560 Macrocells, 216 I/O, RQFP-240 | Altera
EPM9560RC240-1O ⚠ Huling PagbiliPagsanggunian na paghahambing
| Parametro | EPM9560RC240-3 | EPM9560RC240-1O |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Huling Pagbili |
| Device Type | Complex Programmable Logic Device (CPLD) | — |
| Family | MAX 9000 | MAX 9000 |
| Macrocells | 560 | 560 |
| Usable Gates | 12000 | 12,000 |
| Logic Array Blocks (LABs) | 20 | 35 |
| Pin-to-Pin Propagation Delay | 3 ns (speed grade -3) | — |
| Maximum Operating Frequency | [DATA_NEEDED: fMAX] | — |
| Supply Voltage (VCCINT) | 5 V | — |
| Supply Voltage (VCCIO) | 5 V | — |
| User I/O Pins | 192 | — |
| Packhaging | 240-pin RQFP (PowerQuad II) | RQFP-240 (240-pin Reduced-height QFP) |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Configuration Memory | EEPROM (non-volatile) | — |
| Hanay ng Temperature na Operasyon | 0C to +70C (commercial) | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS] | Compliant (per Altera/Intel product page) |
| Lead Finish | [DATA_NEEDED: lead finish] | — |
| Level ng MSL | [DATA_NEEDED: MSL] | — |
| JTAG Support | [DATA_NEEDED: JTAG] | — |
| Maximum User I/O Pins | — | 216 |
| Propagation Delay (tPD) | — | 12 ns (typ, -1 speed grade) |
| Global Setup Time (tFSU) | — | 3.0 ns |
| Clock-to-Output (tFCO) | — | 4.8 ns |
| Maximum Internal Frequency (fCNT) | — | 145 MHz |
| Supply Voltage (VCC) | — | 5.0 V |
| Operating Temperature (Grade) | — | -40C to +85C (industrial, "-1O" suffix) |
| Process Technology | — | CMOS EEPROM, 0.65 um |
| Programming | — | In-system programmable via IEEE 1149.1 JTAG |
| Architecture | — | Multiple Array MatriX (MAX), third generation |
| Lead-Free | — | Yes |