EPM9560RC240-3 vs EPM9560RC240-1O 比較
詳細並排比較 EPM9560RC240-3 由 Altera 與 EPM9560RC240-1O 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Intel
EPM9560RC240-1O - MAX 9000 CPLD, 560 Macrocells, 216 I/O, RQFP-240 | Altera
EPM9560RC240-1O ⚠ 最後購買機會規格比較
| 參數 | EPM9560RC240-3 | EPM9560RC240-1O |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | 最後購買 |
| Device Type | Complex Programmable Logic Device (CPLD) | — |
| Family | MAX 9000 | MAX 9000 |
| Macrocells | 560 | 560 |
| Usable Gates | 12000 | 12,000 |
| Logic Array Blocks (LABs) | 20 | 35 |
| Pin-to-Pin Propagation Delay | 3 ns (speed grade -3) | — |
| Maximum Operating Frequency | [DATA_NEEDED: fMAX] | — |
| Supply Voltage (VCCINT) | 5 V | — |
| Supply Voltage (VCCIO) | 5 V | — |
| User I/O Pins | 192 | — |
| 封裝 | 240-pin RQFP (PowerQuad II) | RQFP-240 (240-pin Reduced-height QFP) |
| 安裝類型 | Surface Mount | Surface Mount |
| Configuration Memory | EEPROM (non-volatile) | — |
| 工作溫度範圍 | 0C to +70C (commercial) | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS] | Compliant (per Altera/Intel product page) |
| Lead Finish | [DATA_NEEDED: lead finish] | — |
| MSL 等級 | [DATA_NEEDED: MSL] | — |
| JTAG Support | [DATA_NEEDED: JTAG] | — |
| Maximum User I/O Pins | — | 216 |
| Propagation Delay (tPD) | — | 12 ns (typ, -1 speed grade) |
| Global Setup Time (tFSU) | — | 3.0 ns |
| Clock-to-Output (tFCO) | — | 4.8 ns |
| Maximum Internal Frequency (fCNT) | — | 145 MHz |
| Supply Voltage (VCC) | — | 5.0 V |
| Operating Temperature (Grade) | — | -40C to +85C (industrial, "-1O" suffix) |
| Process Technology | — | CMOS EEPROM, 0.65 um |
| Programming | — | In-system programmable via IEEE 1149.1 JTAG |
| Architecture | — | Multiple Array MatriX (MAX), third generation |
| Lead-Free | — | Yes |