TD1205 vs SN65LVDS105PWR Perbandingan

Perbandingan bersamaan detil TD1205 dari TD next dan SN65LVDS105PWR dari Texas Instruments. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.

Texas Instruments
SN65LVDS105PWR SN65LVDS105PWR - 1:4 LVDS Clock Fanout Buffer 400Mbps | TI

SN65LVDS105PWR - 1:4 LVDS Clock Fanout Buffer 400Mbps | TI

SN65LVDS105PWR ✓ Aktif

Perbandingan Spesifikasi

Parameter Umum TD1205 SN65LVDS105PWR
Merek TD next Texas Instruments
Kategori RF Modules Clock & Timing
Status Lingkungan Hidup Aktif Aktif
Product Type Sigfox-certified RF transceiver module —
Manufacturer TD next (Telecom Design) —
RF Protocol Sigfox (Ultra-Narrow-Band LPWAN) —
Operating Frequency (RC1) 868 MHz (ETSI Europe) —
Operating Frequency (RC2) 902-928 MHz (US, Australia, Japan) —
Tx Power (RC1) +14 dBm typical —
Tx Power (RC2) +22 dBm maximum —
Receiver Sensitivity [DATA_NEEDED: receiver sensitivity] —
Integrated Microcontroller ARM Cortex-M0+ (STM32 family) —
Clock Reference Integrated TCXO —
Host Interface UART, SPI, I2C, GPIO —
Modulation Ultra-Narrow-Band (UNB), DBPSK uplink —
Maximum Payload Size 12 bytes per uplink message —
Tegangan Pemuat [DATA_NEEDED: VBAT operating range] 3 V to 3.6 V (typical 3.3 V)
Suhu Kerja -40C to +85C [DATA_NEEDED: operating temperature range]
Form Factor Surface-mount LGA castellation module —
Tipe Mounting Surface Mount (reflow) Surface Mount
Status RoHS Compliant —
Fungsi — 1 LVTTL input to 4 LVDS output repeater / fanout buffer
Laju Data — 400 Mbps
Max Clock Frequency — 400 MHz
Input Type — LVTTL (single-ended)
Tipe Output — LVDS (differential), 4 pairs
Output Voltage (typical) — 350 mV into 100 ohm load
Standard Compliance — ANSI EIA/TIA-644 LVDS
Kanal — 1 x 1:4
Paket — 16-TSSOP (PW)
Technology — LVDS differential signaling
Kategori — Signal Buffers, Repeaters, Splitters - Clock Buffer
Arus Memerintah — [DATA_NEEDED: quiescent current]
Input Rise/Fall Time Note — TTL/CMOS rise/fall < 500 ps may require low-Dk laminate per TI layout guidance

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