MCP6S28-I/SL 完全ガイド：8チャネル 12 MHz SPI プログラマブルゲインアンプ — 仕様、ピン配置、代替品、調達（2026年）

The Microchip Technology MCP6S28-I/SL is an 8-channel, single-ended programmable gain amplifier (PGA) with a 12 MHz gain-bandwidth product, SPI-programmable channel and gain selection, and a 16-pin SOIC package. It provides eight gain settings from +1 to +32 V/V with ±1% maximum gain accuracy and ±275 µV maximum input offset voltage on a single 2.5 V to 5.5 V supply with rail-to-rail input and output. Lifecycle status is active, XAIPART stock shows 99,999 units at MOQ 1, and verified tier pricing runs from $4.07 at qty 1 to $2.10 at qty 1000 as of 2026-10-06.

Quick Answers: What Is the MCP6S28-I/SL and What Does It Deliver?

The MCP6S28-I/SL puts an 8-to-1 single-ended input multiplexer, a switched-capacitor gain stage with eight software-selectable gains, and an SPI-compatible control port into one 16-pin SOIC. In a multi-channel data-acquisition front end it replaces a bank of analog switches plus a precision gain resistor network, and it lets firmware re-scale each sensor channel to match an ADC's full-scale input without manual calibration. Channel and gain are written over SPI at clock rates up to 10 MHz; the part is rated -40 °C to +85 °C industrial, carries MSL level 1 (unlimited floor life), and is RoHS compliant.

Takeaway: if your design multiplexes four or more analog sensors into one ADC and needs gain changed from firmware, the MCP6S28-I/SL is active, in stock (99,999 units, MOQ 1), and $2.10 per unit at 1,000 pieces as of 2026-10-06.

Technical Guide: How Do You Design In the MCP6S28-I/SL?

How does the SPI port set channel and gain?

Three pins carry the serial interface: CS on pin 12 (active low), SCK on pin 13, and SI on pin 14. The port is SPI-compatible at clock rates up to 10 MHz — fast enough to change channel and gain between consecutive ADC conversions in a scanning loop. Eight single-ended inputs, IN0 through IN7 on pins 1 through 8, feed the internal 8-to-1 multiplexer, so one PGA services eight sensors through one chip-select line. Dedicate a GPIO to CS, share SCK and SI with the rest of the bus, and keep the CS trace short; there are no address pins to strap because the part is selected by CS alone.

What offset error should you budget at each gain setting?

Multiply the ±275 µV maximum input offset by the selected gain to get worst-case output offset: 275 µV at +1 V/V, 1.1 mV at +4 V/V, 2.75 mV at +10 V/V, and 8.8 mV at +32 V/V. Two statements in the verified record point in different directions, and both should be read at face value. The design guidance states that ±275 µV at the input keeps system offset error well below the LSB size of most 12-bit and 16-bit ADCs. Arithmetic from the same verified specs shows that holds only at low gain: a 12-bit converter with a 5 V full-scale range has an LSB of 1.22 mV (calculated), so the 8.8 mV output offset at +32 V/V is roughly seven LSBs. The difference is gain, not silicon. Keep the gain at +4 V/V or lower for uncalibrated 12-bit DC accuracy, or plan a firmware offset trim for higher gains.

What closed-loop bandwidth do you get at each gain?

Divide the 12 MHz typical gain-bandwidth product by the gain setting: 12 MHz at +1 V/V, 1.5 MHz at +8 V/V, and 375 kHz at +32 V/V (calculated). Input noise density is 10 nV/√Hz, which integrates to roughly 6.1 µV RMS over the 375 kHz noise bandwidth at maximum gain (calculated). Offset, not noise, dominates DC accuracy; noise becomes the limit only when you run the PGA close to its bandwidth ceiling.

How do you power, decouple, and lay out the part?

VDD is pin 11 and accepts a 2.5 V to 5.5 V single supply; VSS is pin 9. The verified design guidance calls for a clean analog supply with a 0.1 µF decoupling capacitor placed close to the IC. Rail-to-rail input and output lets the device accept signals within millivolts of either rail, which matters in 3.3 V and 5 V microcontroller-based systems where a sensor output sits near ground. MSL level 1 means no bake-out before reflow, and the 3.90 mm-body SOIC-16 keeps the analog front end compact next to the ADC.

How do you drive the output into an ADC or a capacitive load?

OUT is pin 10 and swings rail-to-rail. The verified design guidance warns against driving large capacitive loads directly on the output without a series resistor, because AC impedance overshoot can occur. The same record lists no numeric capacitive-load limit, so size the series resistor against your ADC's sample-and-hold acquisition time and confirm it on the bench. At high gain, the pole formed by that resistor and the ADC sampling capacitor sets settling time long before the 375 kHz closed-loop bandwidth does.

What pairs well with the PGA?

Pair the part with an SPI host — Microchip PIC18 or dsPIC microcontrollers per the verified applications data, or a low-cost 32-bit host such as the LPC804M101JHI33Y Cortex-M0+ MCU — plus a successive-approximation ADC. If your front end instead needs programmable resistance rather than programmable gain, the MCP4651T-103E/ST dual 10 kΩ I2C digital potentiometer covers a different function in the same signal chain.

Takeaway: budget gain against offset before you choose ADC resolution — ±275 µV input offset becomes 8.8 mV at +32 V/V, which exceeds one 12-bit LSB on a 5 V range.

Alternatives & Comparison: Which Parts Drop Into the SOIC-16 Footprint?

Five verified alternatives exist inside the MCP6S21/2/6/8 PGA family, and four of them share the 16-pin SOIC footprint of the MCP6S28-I/SL. Packaging is the only difference for the MCP6S28T-I/SL, which ships on Tape & Reel for automated pick-and-place instead of tube — same die, identical pinout. The MCP6S28-E/SL is the same die again with a -40 °C to +125 °C rating that the base part's -40 °C to +85 °C rating does not cover.

Channel count is the main scaling lever. The MCP6S26-I/SL (6 channels) and MCP6S22-I/SL (2 channels) keep the 16-pin SOIC footprint, the same 1–32 V/V gain settings, and identical SPI behavior, so a design can be scaled down without a layout change. The MCP6S21-I/SN is the exception: one channel in an 8-pin SOIC means a new land pattern. Choose it only when a single gain path is enough and the smaller package saves board area.

Takeaway: move to MCP6S28T-I/SL for reel-fed assembly and MCP6S28-E/SL for 125 °C operation with no schematic change; treat MCP6S21-I/SN as a re-layout, not a drop-in.

Industry Insight: What Is the Lifecycle and Supply Situation?

XAIPART's verified record lists the MCP6S28-I/SL as active, with 99,999 units in stock and an MOQ of 1, so prototype and production pulls come from the same listing without a reel minimum. Verified tier pricing as of 2026-10-06 is $4.07 at qty 1, $3.62 at qty 10, $2.95 at qty 100, $2.51 at qty 500, and $2.10 at qty 1000. Distributor-level availability in the same verified record shows Wolfchip Electronics at 7,480 pieces updated April 22, 2026, and DigiKey listing ships-today availability; lead time is typically same-day for small quantities and 4–6 weeks for production volumes.

Two price points in the verified record disagree, and both are quoted as recorded rather than averaged. LCSC unit pricing is listed at USD 2.6552 per piece as of 2026-10-05, while XAIPART's verified qty-1 tier is $4.07 as of 2026-10-06. They reflect different channels and quantity assumptions, so use the tier table for volume planning and spot-check distributor pricing for one-off buys.

Second-sourcing needs engineering work, not a catalog lookup: the verified FAQ states that Microchip publishes no exact cross-reference from the MCP6S28-I/SL to a competitor 8-channel PGA, because the combination of 8 channels, 12 MHz bandwidth, and SPI-programmed gain in a 16-pin SOIC is differentiated. The realistic alternate path is the pin-compatible MCP6S28T-I/SL or the channel-count family members listed above.

Takeaway: with 99,999 units on hand and a 1-piece MOQ, no buffer stock is needed for prototyping; plan production around the $2.10 qty-1000 tier and confirm the reel option (MCP6S28T-I/SL) with your assembler.

Trends & Outlook: What Should Buyers Watch?

Analog front ends are moving from hardware-set gain to firmware-defined gain. Writing channel and gain over an SPI-compatible port clocked at up to 10 MHz gives a scanning loop room to reconfigure between conversions, and ±1% gain accuracy across eight settings eliminates the matched resistor network that discrete op-amp plus switch designs require. Expect more mux-plus-resistor front ends to collapse into integrated PGAs as MCU-integrated ADCs raise channel counts.

Channel count is the first lever. The family spans 8, 6, 2, and 1 channels across two footprints, so confirm the channel count you actually need before committing PCB area: a 16-pin SOIC for four or more sensors, an 8-pin SOIC for one. Temperature rating is the second lever — the -40 °C to +85 °C grade covers most industrial and medical front ends, while designs that must survive 125 °C need the MCP6S28-E/SL variant, same die and package, wider rating.

Offset calibration at high gain is the third lever. The verified arithmetic is unambiguous: ±275 µV input offset becomes 8.8 mV at +32 V/V, which is about seven LSBs of a 12-bit, 5 V converter (calculated). Systems chasing 16-bit DC accuracy at maximum gain should plan a firmware offset trim instead of assuming the offset disappears at the ADC input. Pair that with the 12 MHz gain-bandwidth product when setting the per-channel gain — closed-loop bandwidth falls to 375 kHz at +32 V/V, which is fine for audio-band and sensor signals and not fine for wideband ones.

Finally, watch packaging and inventory signals rather than price alone. The MCP6S28T-I/SL reel option suits automated assembly, and active lifecycle plus 99,999 units at MOQ 1 as of 2026-10-06 removes the allocation pressure that normally drives second-sourcing. Check the MCP6S28-I/SL product page for live stock, browse the XAIPART component catalog for adjacent signal-chain parts, and follow the XAIPART blog for companion-device guides.

Takeaway: fix channel count and temperature grade first — those two decisions set the part number, while gain range, SPI control, supply range, and package stay constant across the family.