10CL055YU484C6G vs 10CL055YU484I7G 比較
詳細な並列比較: 10CL055YU484C6G メーカー: Altera および 10CL055YU484I7G メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | 10CL055YU484C6G | 10CL055YU484I7G |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | 有効 | 有効 |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $24.38 | $35.10 |
| Family | Cyclone 10 LP | Cyclone 10 LP |
| Logic Elements (LE) | 55,856 | — |
| Embedded Memory Bits | 2,396,160 bits (approximately 2.5 Mb) | 2,396,160 bits |
| Maximum User I/Os | 321 | 321 |
| Embedded 18x18 Multipliers | 156 | — |
| PLLs | 4 | 4 |
| Global Clocks | 20 | — |
| Core Voltage | 1.0 V (typical) | — |
| I/O Voltage Standards | LVDS, LVTTL, LVCMOS, SSTL, HSTL (1.2 V to 3.3 V) | — |
| Speed Grade | 6 (commercial, slowest in family) | -7 (I7, industrial) |
| パッケージ | 484-pin UBGA (19 mm x 19 mm) | 484-ball UBGA (Ultra FineLine BGA), 19 mm x 19 mm |
| Process Technology | TSMC 60 nm low-power | 60 nm low-power CMOS |
| 動作温度 | 0 C to +85 C (commercial, C suffix) | — |
| 実装タイプ | Surface Mount | — |
| MSLレベル | [DATA_NEEDED: MSL level per JEDEC J-STD-020] | 3 (per JEDEC J-STD-020) |
| RoHS ステータス | Compliant | Compliant |
| Lead-Free / Halogen-Free | Yes / [DATA_NEEDED: halogen-free status] | — |
| Configuration Modes | Active Serial (AS), Passive Serial (PS), JTAG | JTAG, AS, PS, FPP |
| Transceivers | None (Cyclone 10 LP family does not include SERDES) | — |
| Hard Memory Controller | Yes (DDR/DDR2/DDR3/LPDDR2 via soft IP) | — |
| Logic Elements | — | 55,856 |
| M9K Memory Blocks | — | 260 |
| DSP Blocks (18x18 multipliers) | — | 156 |
| Global Clock Networks | — | 20 |
| 動作接合温度 | — | -40C to +100C |
| Core Voltage (VCCINT) | — | 1.0V (typical), 1.1V nominal |
| I/O Voltage (VCCIO) | — | 1.2V to 3.3V (bank-dependent) |
| LVDS Data Rate | — | Up to 875 Mbps per channel |