EP2S60F1020C4TT vs EP2S60F1020C4N 比較
詳細な並列比較: EP2S60F1020C4TT メーカー: Intel および EP2S60F1020C4N メーカー: Intel。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EP2S60F1020C4TT | EP2S60F1020C4N |
|---|---|---|
| ブランド | Intel | Intel |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | ラストバイ | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $720.00 | $67.00 |
| Family | Stratix II | Stratix II (EP2S60) |
| Process Technology | 90 nm | 90 nm CMOS |
| Logic Elements | 60,440 | 60,440 |
| Equivalent Logic Elements | 60,440 | — |
| Embedded Memory (bits) | 2,544,192 | 2,544,192 |
| Maximum User I/O | 718 | — |
| DSP Blocks (18x18 multipliers) | [DATA_NEEDED: DSP block count for EP2S60] | — |
| PLLs (Enhanced) | [DATA_NEEDED: PLL count] | — |
| Global Clock Networks | [DATA_NEEDED: global clock count] | — |
| パッケージ | 1020-ball FineLine BGA | 1020-ball FC-FBGA (Fine-pitch Chip-Scale BGA) |
| 実装タイプ | Surface Mount (BGA) | Surface Mount (BGA) |
| 動作接合温度 | 0C to +85C (commercial, C4 speed grade) | — |
| Speed Grade | C4 | — |
| Supply Voltage Core | [DATA_NEEDED: VCCINT nominal] | — |
| Memory Interfaces Supported | DDR/DDR2 SDRAM, QDR II/II+ SRAM | — |
| RoHS ステータス | [DATA_NEEDED: RoHS compliance] | EU RoHS compliant with exemption (per Arrow listing) |
| LE Conversion Note | 60,440 LEs is the legacy 'equivalent LE' figure; modern ALM-based naming differs | — |
| MSLレベル | [DATA_NEEDED: moisture sensitivity level] | — |
| Series | — | Stratix II |
| Adaptive Logic Modules (ALMs) | — | 30,220 (approx.) |
| Logic Array Blocks (LABs) | — | 3,022 |
| Embedded Memory Blocks | — | M512/M4K/M-RAM TriMatrix memory |
| DSP Blocks (18-bit x 18-bit) | — | Up to 48 (24 per DSP block column pair typical) |
| User I/Os | — | 718 |
| Maximum Core Frequency | — | 711.24 MHz (per Arrow listing) |
| Core Voltage | — | 1.2 V |
| Operating Temperature Grade | — | Commercial (C4 suffix indicates commercial, speed grade 4) |
| Configuration Modes | — | Passive Serial, Fast Passive Parallel, JTAG |
| PLLs / Clock Networks | — | Yes - on-chip PLLs and global clock networks |