EP2S60F1020C4TT vs EP2S60F1020C4N 비교
다음의 상세 나란히 비교: EP2S60F1020C4TT 제조: Intel 및 EP2S60F1020C4N 제조: Intel. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
사양 비교
| 파라미터 | EP2S60F1020C4TT | EP2S60F1020C4N |
|---|---|---|
| 브랜드 | Intel | Intel |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | 최종 구매 | Obsolete |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $720.00 | $67.00 |
| Family | Stratix II | Stratix II (EP2S60) |
| Process Technology | 90 nm | 90 nm CMOS |
| Logic Elements | 60,440 | 60,440 |
| Equivalent Logic Elements | 60,440 | — |
| Embedded Memory (bits) | 2,544,192 | 2,544,192 |
| Maximum User I/O | 718 | — |
| DSP Blocks (18x18 multipliers) | [DATA_NEEDED: DSP block count for EP2S60] | — |
| PLLs (Enhanced) | [DATA_NEEDED: PLL count] | — |
| Global Clock Networks | [DATA_NEEDED: global clock count] | — |
| 패키지 | 1020-ball FineLine BGA | 1020-ball FC-FBGA (Fine-pitch Chip-Scale BGA) |
| 실장 유형 | Surface Mount (BGA) | Surface Mount (BGA) |
| 동작 접합 온도 | 0C to +85C (commercial, C4 speed grade) | — |
| Speed Grade | C4 | — |
| Supply Voltage Core | [DATA_NEEDED: VCCINT nominal] | — |
| Memory Interfaces Supported | DDR/DDR2 SDRAM, QDR II/II+ SRAM | — |
| RoHS 상태 | [DATA_NEEDED: RoHS compliance] | EU RoHS compliant with exemption (per Arrow listing) |
| LE Conversion Note | 60,440 LEs is the legacy 'equivalent LE' figure; modern ALM-based naming differs | — |
| MSL 레벨 | [DATA_NEEDED: moisture sensitivity level] | — |
| Series | — | Stratix II |
| Adaptive Logic Modules (ALMs) | — | 30,220 (approx.) |
| Logic Array Blocks (LABs) | — | 3,022 |
| Embedded Memory Blocks | — | M512/M4K/M-RAM TriMatrix memory |
| DSP Blocks (18-bit x 18-bit) | — | Up to 48 (24 per DSP block column pair typical) |
| User I/Os | — | 718 |
| Maximum Core Frequency | — | 711.24 MHz (per Arrow listing) |
| Core Voltage | — | 1.2 V |
| Operating Temperature Grade | — | Commercial (C4 suffix indicates commercial, speed grade 4) |
| Configuration Modes | — | Passive Serial, Fast Passive Parallel, JTAG |
| PLLs / Clock Networks | — | Yes - on-chip PLLs and global clock networks |