EP910JC-30 vs EP910PI-20 比較
詳細な並列比較: EP910JC-30 メーカー: Intel および EP910PI-20 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EP910JC-30 | EP910PI-20 |
|---|---|---|
| ブランド | Intel | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $9.75 | $9.75 |
| Family | Classic EPLD (MAX-style) | — |
| Propagation Delay (tpd) | 30 ns | — |
| Maximum Internal Frequency (Fmax) | 33.3 MHz | — |
| Macrocells | 24 | 24 |
| Inputs | 36 | — |
| Product Terms | 240 | — |
| Outputs | 10 dedicated | — |
| Supply Voltage (Vcc) | 5 V | — |
| Technology | CMOS EPROM, UV-erasable | CMOS EPROM (UV-erasable windowed variants available) |
| パッケージ | 44-pin Windowed Ceramic J-Lead Chip Carrier (CQCC-44 / JLCC-44) | PDIP-40 (PI suffix) |
| 動作温度 | [DATA_NEEDED: operating temperature range] | -40C to +85C (industrial) |
| Supply Current (Icc) | [DATA_NEEDED: Icc typical / maximum] | — |
| 実装タイプ | Surface Mount (socket-mountable) | Through-Hole |
| RoHS ステータス | [DATA_NEEDED: RoHS compliance] | unknown |
| Logic Blocks | 24 macrocells (AND/OR array architecture) | — |
| Device Family | — | Altera Classic EPLD Family |
| Propagation Delay (tPD) | — | 20 ns |
| Supply Voltage (VCC) | — | 5 V (+/- 5%) |
| Configuration Method | — | Non-volatile EPROM (no boot PROM required) |
| Dedicated Inputs | — | 12 |
| Bidirectional I/O Pins | — | 24 |
| Maximum Counter Frequency | — | 125 MHz |
| Output Drive Current (IOL) | — | 24 mA (TTL-compatible) |
| Programmable Polarity | — | Yes (XOR gate per macrocell) |
| Macrocell Flip-Flop | — | Yes (D-type, programmable) |
| Power Dissipation | — | [DATA_NEEDED: typical power dissipation in mW] |
| Programming Interface | — | JEDEC file via Altera programming hardware |
| MIL-STD-883 Variant | — | EP910DM/883B (separate part number) |