EPC1LI20 vs EPC2LI20 比較
詳細な並列比較: EPC1LI20 メーカー: Altera および EPC2LI20 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPC1LI20 | EPC2LI20 |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | Memory ICs | Memory ICs |
| ライフサイクル状態 | Obsolete | NRND |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $8.50 | $5.95 |
| メモリタイプ | OTP Configuration PROM (EPROM-based) | Flash (in-system programmable) |
| メモリサイズ | 1 Mb (1,048,576 bits) | 1.6 Mb (1,572,864 bits) |
| Configuration Interface | Altera Passive Serial / Altera Active Serial / JTAG (IEEE 1149.1) | Serial or Byte-wide (parallel) |
| Maximum Configuration Clock | 8 MHz | — |
| Supply Voltage (VCC) | 5.0 V (4.75 V to 5.25 V) | — |
| Programming Voltage (VPP) | 12.75 V (typical, factory-programmed via JTAG) | — |
| パッケージ | 20-pin PLCC (J-lead, 9x9 mm) | — |
| ピン数 | 20 | — |
| 動作温度 | [DATA_NEEDED: operating temperature range] | -40 C to +85 C (Industrial) |
| Cascading Support | Yes (nCASC pin for multi-device daisy chain) | — |
| Endurance | OTP (one-time programmable, 1000 erase-equivalent UV cycles for pre-program erase) | — |
| JTAG Programming | Yes (in-system via IEEE 1149.1) | — |
| Compatible FPGA Families | FLEX 8000, FLEX 10K, ACEX 1K, APEX 20K, Mercury | — |
| 実装タイプ | Surface Mount (PLCC socket compatible) | Surface Mount (PLCC socket-compatible) |
| MSLレベル | 1 (per Partstack datasheet record) | [DATA_NEEDED: MSL level] |
| RoHS ステータス | [DATA_NEEDED: RoHS status - original Altera part may be non-RoHS SnPb finish] | [DATA_NEEDED: RoHS status] |
| Programmable Type | — | In System Programmable (ISP) |
| 機能 | — | Configuration PROM for SRAM-based FPGAs |
| Supply Voltage - Operating | — | 3.0 V to 3.6 V and 4.5 V to 5.5 V (auto-sensing) |
| パッケージ / ケース | — | 20-PLCC (J-lead, 9x9 mm) |
| Decompression | — | On-chip (supports compressed bitstreams) |
| JTAG / ISP Interface | — | IEEE 1532 (TCK, TMS, TDI, TDO) |
| Multi-Device Support | — | Yes (daisy-chain configuration) |
| User-Accessible Memory | — | Yes (unused flash available to user logic) |