EPM5032DI-20 vs EPM5032DC-20 比較
詳細な並列比較: EPM5032DI-20 メーカー: Intel および EPM5032DC-20 メーカー: Intel。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPM5032DI-20 | EPM5032DC-20 |
|---|---|---|
| ブランド | Intel | Intel |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $8.75 | $5.05 |
| Family | MAX 5000 (Altera legacy EPLD) | — |
| Architecture | CMOS PAL-type EPLD with PIA | — |
| Macrocells | 32 | 32 |
| Dedicated Inputs | 7 | — |
| Bidirectional I/O Pins | 16 | — |
| Product Terms | 320 (maximum) | — |
| Flip-Flops | 16 (one per macrocell) | — |
| 最大クロック周波数 | 62.5 MHz | — |
| Pin-to-Pin Delay | 20 ns (speed grade -20) | — |
| パッケージ | Ceramic DIP-20 (windowed, UV-erasable) | 20-pin DIP (Windowed Ceramic, 0.3" wide) |
| 動作温度 | Industrial (per 'I' suffix) | [DATA_NEEDED: commercial/industrial/military grade] |
| Programming | UV-erasable CMOS, JEDEC fuse file | — |
| Development Tool | Altera MAX+PLUS II (legacy) | — |
| RoHS ステータス | [DATA_NEEDED: RoHS compliance status for ceramic DIP variant] | Compliant (per IC-Components listing) |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Product Family | — | MAX 5000 |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Programmable Technology | — | UV-Erasable / OTP EPROM |
| Usable Gates | — | 600 |
| Maximum Frequency (fCNT) | — | 71.4 MHz |
| Pin-to-Pin Delay (tPD) | — | 20 ns |
| Speed Grade | — | -20 |
| Supply Voltage (VCC) | — | 5 V |
| 実装タイプ | — | Through-Hole |
| Logic Blocks | — | 4 Logic Array Blocks (LABs) |
| I/O Pins | — | [DATA_NEEDED: I/O pin count for DIP-20 variant] |
| Lead Free | — | [DATA_NEEDED: confirmed lead-free] |
| Manufacturer | — | Altera (now Intel Programmable Solutions Group) |
| Programming Method | — | Altera MAX+PLUS II / Quartus (legacy support) |