EPM5192AJC-25 vs EPM5192AJC-15 比較
詳細な並列比較: EPM5192AJC-25 メーカー: Altera および EPM5192AJC-15 メーカー: Intel。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPM5192AJC-25 | EPM5192AJC-15 |
|---|---|---|
| ブランド | Altera | Intel |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | NRND |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $8.20 | $9.85 |
| Family | MAX 5000 EPLD | MAX 5000 |
| Manufacturer | Altera (now Intel PSG) | — |
| Macrocells | 192 | 192 |
| Propagation Delay (tPD) | 25 ns | — |
| パッケージ | PLCC-68 (windowed ceramic, AJC) | 84-pin PLCC (J-lead, ceramic, non-windowed) |
| ピン数 | 68 | 84 |
| 実装タイプ | Surface Mount | Surface Mount |
| 電源電圧 | 5 V (typical) | — |
| Logic Blocks | MAX 5000 LABs (Logic Array Blocks) | — |
| Programmable Pins | [DATA_NEEDED: number of user I/O pins] | — |
| 動作温度 | [DATA_NEEDED: exact operating temperature range] | 0C to +70C (commercial) |
| Erasure Method | UV-erasable (windowed ceramic package) | — |
| Programming Technology | EPROM (non-volatile) | — |
| RoHS ステータス | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS compliance] |
| Military Grade | Likely MIL-STD-883 processing per 'J' suffix in AJC marking (verify) | — |
| Device Type | — | EPLD (Erasable Programmable Logic Device) |
| Logic Capacity | — | 100% connectivity, sum-of-products PLA architecture |
| Pin-to-Pin Delay (tPD) | — | 15 ns |
| Supply Voltage (VCC) | — | 5 V (4.75 V to 5.25 V) |
| Programmability | — | UV-erasable (windowed variant) / One-Time-Programmable |
| Toolchain | — | MAX+PLUS II |
| User I/O Pins | — | [DATA_NEEDED: user I/O count] |
| Speed Grades Available | — | -15, -20, -25 (this part: -15) |
| Configuration Memory | — | EPROM (UV-erasable) |