EPM5192AJC-25 vs EPM5192AJC-15 비교
다음의 상세 나란히 비교: EPM5192AJC-25 제조: Altera 및 EPM5192AJC-15 제조: Intel. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
사양 비교
| 파라미터 | EPM5192AJC-25 | EPM5192AJC-15 |
|---|---|---|
| 브랜드 | Altera | Intel |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | Obsolete | NRND |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $8.20 | $9.85 |
| Family | MAX 5000 EPLD | MAX 5000 |
| Manufacturer | Altera (now Intel PSG) | — |
| Macrocells | 192 | 192 |
| Propagation Delay (tPD) | 25 ns | — |
| 패키지 | PLCC-68 (windowed ceramic, AJC) | 84-pin PLCC (J-lead, ceramic, non-windowed) |
| 핀 수 | 68 | 84 |
| 실장 유형 | Surface Mount | Surface Mount |
| 공급 전압 | 5 V (typical) | — |
| Logic Blocks | MAX 5000 LABs (Logic Array Blocks) | — |
| Programmable Pins | [DATA_NEEDED: number of user I/O pins] | — |
| 동작 온도 | [DATA_NEEDED: exact operating temperature range] | 0C to +70C (commercial) |
| Erasure Method | UV-erasable (windowed ceramic package) | — |
| Programming Technology | EPROM (non-volatile) | — |
| RoHS 상태 | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS compliance] |
| Military Grade | Likely MIL-STD-883 processing per 'J' suffix in AJC marking (verify) | — |
| Device Type | — | EPLD (Erasable Programmable Logic Device) |
| Logic Capacity | — | 100% connectivity, sum-of-products PLA architecture |
| Pin-to-Pin Delay (tPD) | — | 15 ns |
| Supply Voltage (VCC) | — | 5 V (4.75 V to 5.25 V) |
| Programmability | — | UV-erasable (windowed variant) / One-Time-Programmable |
| Toolchain | — | MAX+PLUS II |
| User I/O Pins | — | [DATA_NEEDED: user I/O count] |
| Speed Grades Available | — | -15, -20, -25 (this part: -15) |
| Configuration Memory | — | EPROM (UV-erasable) |