EPM5192JC-ES vs EPM5192JC2 比較
詳細な並列比較: EPM5192JC-ES メーカー: Intel および EPM5192JC2 メーカー: Intel。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPM5192JC-ES | EPM5192JC2 |
|---|---|---|
| ブランド | Intel | Intel |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $16.45 | $15.90 |
| Device Family | MAX 5000 | — |
| Device Type | CPLD (EPLD) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 192 | 192 |
| Logic Array Blocks (LABs) | 12 | 12 |
| Interconnect | Programmable Interconnect Array (PIA) | Programmable Interconnect Array (PIA) |
| Configuration Memory | EPROM (UV-erasable, one-time programmable for JC-ES) | — |
| パッケージ | 84-pin PLCC (J-lead, CQCC, JEDEC S-CQCC-J84) | PLCC-68 (JC) |
| 実装タイプ | Surface Mount | Surface Mount (socketable PLCC) |
| Technology | CMOS | — |
| Programming | Altera MAX+PLUS II or compatible programmer | Altera Master Programmer / ByteBlaster via JTAG-style interface |
| 動作温度 | [DATA_NEEDED: operating temperature range for ES grade] | — |
| 電源電圧 | [DATA_NEEDED: VCC nominal] | — |
| User I/O Pins | [DATA_NEEDED: user I/O count for JC-ES in PLCC-84] | — |
| RoHS ステータス | [DATA_NEEDED: RoHS compliance] | — |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| MSLレベル | [DATA_NEEDED: MSL rating] | — |
| Note | Datasheet source: Altera MAX 5000 family document, 52 pages | — |
| Family | — | MAX 5000 |
| Usable Gates (equivalent) | — | 6000 |
| Maximum User I/O | — | 64 |
| Dedicated Inputs | — | 7 |
| External Clock Inputs | — | 1 (with shared input/clock capability) |
| 最大クロック周波数 | — | 50 MHz |
| Propagation Delay (tPD) | — | 45 ns (speed grade -2) |
| Process Technology | — | CMOS, UV-erasable |