EPM5192JC-ES vs EPM5192JC2 비교
다음의 상세 나란히 비교: EPM5192JC-ES 제조: Intel 및 EPM5192JC2 제조: Intel. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
사양 비교
| 파라미터 | EPM5192JC-ES | EPM5192JC2 |
|---|---|---|
| 브랜드 | Intel | Intel |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | Obsolete | Obsolete |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $16.45 | $15.90 |
| Device Family | MAX 5000 | — |
| Device Type | CPLD (EPLD) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 192 | 192 |
| Logic Array Blocks (LABs) | 12 | 12 |
| Interconnect | Programmable Interconnect Array (PIA) | Programmable Interconnect Array (PIA) |
| Configuration Memory | EPROM (UV-erasable, one-time programmable for JC-ES) | — |
| 패키지 | 84-pin PLCC (J-lead, CQCC, JEDEC S-CQCC-J84) | PLCC-68 (JC) |
| 실장 유형 | Surface Mount | Surface Mount (socketable PLCC) |
| Technology | CMOS | — |
| Programming | Altera MAX+PLUS II or compatible programmer | Altera Master Programmer / ByteBlaster via JTAG-style interface |
| 동작 온도 | [DATA_NEEDED: operating temperature range for ES grade] | — |
| 공급 전압 | [DATA_NEEDED: VCC nominal] | — |
| User I/O Pins | [DATA_NEEDED: user I/O count for JC-ES in PLCC-84] | — |
| RoHS 상태 | [DATA_NEEDED: RoHS compliance] | — |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| MSL 레벨 | [DATA_NEEDED: MSL rating] | — |
| Note | Datasheet source: Altera MAX 5000 family document, 52 pages | — |
| Family | — | MAX 5000 |
| Usable Gates (equivalent) | — | 6000 |
| Maximum User I/O | — | 64 |
| Dedicated Inputs | — | 7 |
| External Clock Inputs | — | 1 (with shared input/clock capability) |
| 최대 클록 주파수 | — | 50 MHz |
| Propagation Delay (tPD) | — | 45 ns (speed grade -2) |
| Process Technology | — | CMOS, UV-erasable |