EPM5192LC-35 vs EPM5192LC-2N 比較
詳細な並列比較: EPM5192LC-35 メーカー: Altera および EPM5192LC-2N メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPM5192LC-35 | EPM5192LC-2N |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $15.25 | $11.85 |
| Series | MAX 5000 | — |
| Family | MAX 5000 CPLD | MAX 5000 |
| Logic Elements / Macrocells | 192 macrocells | — |
| Pin-to-Pin Delay (tPD) | 35 ns | — |
| Speed Grade | -35 | -2 (tPD approximately 25 ns) |
| Programmable Type | UV-Erasable / OTP (EPROM-based) | — |
| Package Type | JLCC (J-Lead Ceramic Chip Carrier) | LC (ceramic J-leaded, windowed UV-erasable package family) |
| 実装タイプ | Surface Mount | Surface Mount (LC package) |
| Logic Voltage | 5 V TTL-compatible I/O | — |
| 動作温度 | Commercial (0C to +70C) per LC suffix | Commercial (0C to +70C) - inferred from speed-grade -2 designation |
| Programming Method | Altera legacy programmer (EPROM-based) | — |
| Architecture | LAB-based with Programmable Interconnect Array (PIA) | Programmable Logic Array (PLA) with global PIA |
| I/O Standard | TTL | — |
| RoHS ステータス | Non-compliant (ceramic hermetic package) | Compliant (per -N lead-free suffix) |
| ライフサイクル状態 | Obsolete - last-time-buy stock only | — |
| Datasheet Document | Altera MAX 5000 family datasheet (per alldatasheet.com) | — |
| Macrocells | — | 192 |
| Flip-Flops | — | 192 |
| Logic Elements | — | 192 macrocells (PAL/GAL-style AND-OR array) |
| Propagation Delay (typical) | — | 25 ns |
| 電源電圧 | — | 5 V (typical) |
| Programmability | — | UV-erasable EPROM cell |
| Lead-Free | — | Yes (per -N suffix) |
| Programming Interface | — | Altera programming hardware (MAX+PLUS II / ByteBlaster compatible) |