EPM5192LC-35 vs EPM5192LC-2N Comparison
Detailed side-by-side comparison of EPM5192LC-35 by Altera and EPM5192LC-2N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM5192LC-35 | EPM5192LC-2N |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Series | MAX 5000 | — |
| Family | MAX 5000 CPLD | MAX 5000 |
| Logic Elements / Macrocells | 192 macrocells | — |
| Pin-to-Pin Delay (tPD) | 35 ns | — |
| Speed Grade | -35 | -2 (tPD approximately 25 ns) |
| Programmable Type | UV-Erasable / OTP (EPROM-based) | — |
| Package Type | JLCC (J-Lead Ceramic Chip Carrier) | LC (ceramic J-leaded, windowed UV-erasable package family) |
| Mounting Type | Surface Mount | Surface Mount (LC package) |
| Logic Voltage | 5 V TTL-compatible I/O | — |
| Operating Temperature | Commercial (0C to +70C) per LC suffix | Commercial (0C to +70C) - inferred from speed-grade -2 designation |
| Programming Method | Altera legacy programmer (EPROM-based) | — |
| Architecture | LAB-based with Programmable Interconnect Array (PIA) | Programmable Logic Array (PLA) with global PIA |
| I/O Standard | TTL | — |
| RoHS Status | Non-compliant (ceramic hermetic package) | Compliant (per -N lead-free suffix) |
| Lifecycle Status | Obsolete - last-time-buy stock only | — |
| Datasheet Document | Altera MAX 5000 family datasheet (per alldatasheet.com) | — |
| Macrocells | — | 192 |
| Flip-Flops | — | 192 |
| Logic Elements | — | 192 macrocells (PAL/GAL-style AND-OR array) |
| Propagation Delay (typical) | — | 25 ns |
| Supply Voltage | — | 5 V (typical) |
| Programmability | — | UV-erasable EPROM cell |
| Lead-Free | — | Yes (per -N suffix) |
| Programming Interface | — | Altera programming hardware (MAX+PLUS II / ByteBlaster compatible) |