EPM9320ALC84-10 - MAX 9000 CPLD, 320 Macrocells, 84-PLCC | Intel
部品番号: EPM9320ALC84-10 ✗ 生産終了| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $38.5 | $38.50 |
| 10 | $34.65 | $346.50 |
| 100 | $28.4 | $2,840.00 |
| 500 | $23.75 | $11,875.00 |
| 1,000 | $19.8 | $19,800.00 |
EPM9320ALC84-10 概要
A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines multiple PAL-like logic blocks on a single chip with a central interconnect matrix. CPLDs sit between simple SPLDs (e.g. PAL/GAL) and larger FPGAs in the programmable logic hierarchy: SPLD -> CPLD -> FPGA -> programmable logic -> digital IC -> semiconductor. The MAX 9000 architecture targets high-density glue logic, bus-interface bridging, and state-machine control with deterministic timing that is critical for system-level design.
Key features include 320 macrocells (organized across 16 Logic Array Blocks, LABs), 16 dedicated inputs, 52 I/O pins in the 84-PLCC, and PCI Local Bus Specification Revision 2.2 compliance for the -10 speed grade. Each macrocell contains a programmable register with configurable Product-Term allocation, allowing wide combinational and registered logic functions. The 5.0-V ISP interface enables board-level programming via JTAG, eliminating socketed pre-programmed parts and supporting field upgrades.
The MAX architecture uses a continuous, central interconnect called the FastTrack Interconnect, providing predictable delay paths between LABs. Compared with smaller MAX 7000 devices, the MAX 9320 doubles logic capacity, and the -10 speed grade is suitable for 33 MHz PCI bus interfaces. The EEPROM-based configuration cell is non-volatile, so the device powers up in a known state with no external boot PROM required, simplifying board bring-up.
Typical applications include PCI bus interface glue logic, peripheral controllers for embedded microprocessors, bus protocol translation (e.g., ISA-to-PCI bridges), industrial control state machines, and legacy 5-V system glue logic where deterministic timing and high I/O count are required. Designers choose this part over FPGAs when they need non-volatile, instant-on logic and a deterministic 10 ns timing model.
When designing with the EPM9320ALC84-10, observe the PCI 2.2 AC switching characteristics for the -10 speed grade and derate the toggle frequency according to the Power-Down Current vs. Frequency graph in the device family datasheet. The 84-PLCC socket is recommended for prototypes and field upgrades because ISP can be done directly on the board via the JTAG pins. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet.
ドロップイン代替品: EPM9320ALC84-10 — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: EPM9320ALC84-10 （同一形状・フットプリント） — 相違点: Package, Mounting Type, Architecture, Process Technology, Supply Voltage (VCC).
クイック比較ツール — 並列比較する代替部品を選択:
EPM9320ALI84-10
✅ ドロップイン✓ 在庫あり
$19.95 / 個
データシートを見る →EPM9320LC84-15
✅ ドロップイン✓ 在庫あり
$17.95 / 個
データシートを見る →EPM9320LC84-10
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$84.96 / 個
データシートを見る →EPM9320ALC84-10N
✅ ドロップイン✓ 在庫あり
$21.4 / 個
データシートを見る →EPM9320ALC84-10 最大定格＆電気的特性
| Family | MAX 9000 |
| Device | EPM9320 |
| Macrocells | 320 |
| Logic Array Blocks (LABs) | 16 |
| Maximum User I/O Pins | 52 |
| Dedicated Inputs | 16 |
| Speed Grade | -10 (10 ns pin-to-pin delay) |
| Pin-to-Pin Delay (tPD) | 10 ns |
| Supply Voltage (VCCINT) | 5.0 V |
| In-System Programmability | 5.0 V ISP via IEEE 1149.1 JTAG |
| Technology | CMOS EEPROM-based, third-generation MAX |
| PCI Compliance | PCI Local Bus Specification Rev. 2.2 (speed grade -10) |
| パッケージ | 84-pin PLCC (J-Lead) |
| 実装タイプ | Surface Mount / Through-Hole (PLCC socket) |
| Non-Volatile Configuration | Yes (EEPROM cell, powers up in known state) |
| Architecture | MAX (Multiple Array MatriX) with FastTrack Interconnect |
EPM9320ALC84-10 ピン構成
| ピン 1 | I/O — User I/O pin (Macrocells / LAB interconnect) |
| ピン 2 | I/O — User I/O pin |
| ピン 3 | I/O — User I/O pin |
| ピン 4 | I/O — User I/O pin |
| ピン 5 | I/O — User I/O pin |
| ピン 6 | I/O — User I/O pin |
| ピン 7 | VCCINT — 5.0 V core supply |
| ピン 8 | I/O — User I/O pin |
| ピン 9 | I/O — User I/O pin |
| ピン 10 | I/O — User I/O pin |
| ピン 11 | GND — Ground |
| ピン 12 | I/O — User I/O pin |
| ピン 13 | I/O — User I/O pin |
| ピン 14 | TDI — JTAG Test Data In |
| ピン 15 | TMS — JTAG Test Mode Select |
| ピン 16 | TCK — JTAG Test Clock |
| ピン 17 | I/O — User I/O pin |
| ピン 18 | I/O — User I/O pin |
| ピン 19 | I/O — User I/O pin |
| ピン 20 | I/O — User I/O pin |
| ピン 21 | I/O — User I/O pin |
| ピン 22 | VCCIO — 5.0 V I/O supply |
| ピン 23 | I/O — User I/O pin |
| ピン 24 | I/O — User I/O pin |
| ピン 25 | I/O — User I/O pin |
| ピン 26 | I/O — User I/O pin |
| ピン 27 | GND — Ground |
| ピン 28 | I/O — User I/O pin |
| ピン 29 | I/O — User I/O pin |
| ピン 30 | I/O — User I/O pin |
| ピン 31 | I/O — User I/O pin |
| ピン 32 | I/O — User I/O pin |
| ピン 33 | I/O — User I/O pin |
| ピン 34 | I/O — User I/O pin |
| ピン 35 | I/O — User I/O pin |
| ピン 36 | I/O — User I/O pin |
| ピン 37 | VCCINT — 5.0 V core supply |
| ピン 38 | I/O — User I/O pin |
| ピン 39 | I/O — User I/O pin |
| ピン 40 | I/O — User I/O pin |
| ピン 41 | GND — Ground |
| ピン 42 | INPUT/GCLK — Dedicated input / Global Clock |
| ピン 43 | INPUT/GCLK — Dedicated input / Global Clock |
| ピン 44 | INPUT/GCLK — Dedicated input / Global Clock |
| ピン 45 | INPUT — Dedicated input pin |
| ピン 46 | INPUT — Dedicated input pin |
| ピン 47 | INPUT — Dedicated input pin |
| ピン 48 | INPUT — Dedicated input pin |
| ピン 49 | I/O — User I/O pin |
| ピン 50 | I/O — User I/O pin |
| ピン 51 | I/O — User I/O pin |
| ピン 52 | I/O — User I/O pin |
| ピン 53 | I/O — User I/O pin |
| ピン 54 | VCCIO — 5.0 V I/O supply |
| ピン 55 | I/O — User I/O pin |
| ピン 56 | I/O — User I/O pin |
| ピン 57 | I/O — User I/O pin |
| ピン 58 | I/O — User I/O pin |
| ピン 59 | I/O — User I/O pin |
| ピン 60 | GND — Ground |
| ピン 61 | I/O — User I/O pin |
| ピン 62 | I/O — User I/O pin |
| ピン 63 | I/O — User I/O pin |
| ピン 64 | I/O — User I/O pin |
| ピン 65 | I/O — User I/O pin |
| ピン 66 | I/O — User I/O pin |
| ピン 67 | I/O — User I/O pin |
| ピン 68 | I/O — User I/O pin |
| ピン 69 | I/O — User I/O pin |
| ピン 70 | VCCINT — 5.0 V core supply |
| ピン 71 | I/O — User I/O pin |
| ピン 72 | I/O — User I/O pin |
| ピン 73 | I/O — User I/O pin |
| ピン 74 | GND — Ground |
| ピン 75 | I/O — User I/O pin |
| ピン 76 | I/O — User I/O pin |
| ピン 77 | I/O — User I/O pin |
| ピン 78 | I/O — User I/O pin |
| ピン 79 | I/O — User I/O pin |
| ピン 80 | I/O — User I/O pin |
| ピン 81 | I/O — User I/O pin |
| ピン 82 | I/O — User I/O pin |
| ピン 83 | TDO — JTAG Test Data Out |
| ピン 84 | I/O — User I/O pin |
主な用途
EPM9320ALC84-10 の用途: 6 件s: PCI Bus Interface Glue Logic, Embedded Microprocessor Peripheral Controller, Bus Protocol Translation Bridge, Industrial Control State Machine, Legacy 5V System Glue Logic, Field-Upgradeable Control Plane.
PCI Bus Interface Glue Logic
The EPM9320ALC84-10 fits PCI bus interface designs because its -10 speed grade is explicitly compliant with PCI Local Bus Specification Revision 2.2, providing the required AC switching characteristics at 33 MHz. With 320 macrocells and 16 dedicated inputs, the device can implement address decoding, command decoding, and interrupt steering across multiple bus slots in a single chip. The 52 user I/O pins support 32-bit data plus control signals, and the 10 ns tPD ensures deterministic timing across the central FastTrack Interconnect.
おすすめ
Embedded Microprocessor Peripheral Controller
With 320 macrocells, 5.0-V I/O, and JTAG ISP, the EPM9320ALC84-10 fits 8051, x86, or 68k embedded systems that need deterministic peripheral glue logic. The MAX architecture's central FastTrack Interconnect gives predictable tPD, and the non-volatile EEPROM cell eliminates external boot PROMs, simplifying board bring-up. The 84-PLCC package supports socketed prototypes and field upgrades via JTAG, and the 5.0-V tolerance matches TTL logic in industrial 5-V backplanes.
おすすめ
Bus Protocol Translation Bridge
The EPM9320ALC84-10 implements ISA-to-PCI, VME-to-PCI, or PC/104-to-PCI protocol bridges because of its high macrocell count (320), 10 ns tPD, and 52 user I/O pins. A bridge can use LABs for state-machine protocol engines, with the central interconnect carrying control signals between LABs at deterministic delay. The 5.0-V I/O matches legacy 5-V buses directly, and JTAG ISP lets designers field-upgrade protocol firmware without removing the part from the socket.
おすすめ
Industrial Control State Machine
For factory automation, motor control sequencers, and PLC digital sub-systems, the EPM9320ALC84-10 offers the deterministic timing, 5.0-V I/O, and wide temperature operation (via the -I suffix variant) required for industrial environments. The 320 macrocells can encode multi-state control loops, fault-handling state machines, and timing generators in a single device. The MAX 9000 architecture's wide Product-Term allocation supports large fan-in logic, useful for combining sensor inputs into control outputs.
おすすめ
Legacy 5V System Glue Logic
The EPM9320ALC84-10 is purpose-designed for 5-V backplanes, VMEbus, and 5-V PCI systems where 3.3-V or 1.8-V FPGAs cannot interface directly. With 5.0-V VCCINT, 5.0-V tolerant I/O, and 5.0-V ISP via JTAG, it replaces dozens of 74-series TTL glue chips with a single programmable part. Designers use the 320 macrocells to consolidate address decoders, chip-select generators, interrupt arbiters, and bus transceivers - simplifying PCB layout and reducing BOM cost in legacy systems.
おすすめ
Field-Upgradeable Control Plane
Designers deploy the EPM9320ALC84-10 in field-upgradeable control planes where the 5.0-V ISP via JTAG allows remote firmware updates without board removal. The non-volatile EEPROM cell ensures the device powers up in a known state even after power-cycling, and the JTAG interface can be reused for boundary-scan testing during manufacturing. Combined with the 84-PLCC socket, this enables field serviceability for telecom, aerospace, and defense systems where board swap-out is expensive.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: EPM9320ALC84-10 — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | EPM9320ALI84-10 | EPM9320LC84-15 | EPM9320LC84-10 | EPM9320ALC84-10N | EPM9320ARC208-10 |
|---|---|---|---|---|---|---|
| Brand | Intel (formerly Altera) | Intel | Intel | Intel | Intel | Intel |
| Package | 84-pin PLCC | 84-pin PLCC - same | 84-pin PLCC - same | 84-pin PLCC - same | 84-pin PLCC - same | 208-pin RQFP/PQFP - DIFFERENT |
| Speed Grade (tPD) | 10 ns | 10 ns | 15 ns (-50%) | 10 ns | 10 ns | 10 ns |
| Macrocells | 320 | 320 | 320 | 320 | 320 | 320 |
| Logic Array Blocks (LABs) | 16 | 16 | 16 | 16 | 16 | 16 |
| Maximum User I/O | 52 | 52 | 52 | 52 | 52 | higher (~132 in 208-pin) |
| Supply Voltage | 5.0 V | 5.0 V | 5.0 V | 5.0 V | 5.0 V | 5.0 V |
| Temperature Grade | Commercial (0C to +70C) | Industrial (-40C to +85C) | Commercial | Commercial | Commercial | Commercial |
| PCI 2.2 Compliance | Yes (speed grade -10) | Yes (speed grade -10) | Not for -15 speed grade | Yes (speed grade -10) | Yes | Yes |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
主な差別化要因
- Highest speed grade in MAX 9000 family for PCI 2.2 compliance （vs EPM9320LC84-15)
- 320 macrocells - largest density in MAX 9000 PLCC line （vs EPM7256SRC208-10)
- 84-PLCC package suitable for socketed field upgrades （vs EPM9320ARC208-10)
設計ノート
The EPM9320ALC84-10 requires a stable 5.0 V supply on VCCINT and VCCIO pins. Decouple each VCC pin with a 0.1 uF ceramic capacitor placed within 5 mm of the package pin, plus a bulk 10-47 uF tantalum or electrolytic capacitor at the board supply entry. The device draws typical ICC in the 100-300 mA range during operation, depending on toggle frequency; consult the MAX 9000 family datasheet Power Consumption vs. Frequency graph. Estimated: with 50% I/O toggle at 33 MHz and all 320 macrocells enabled, ICC may approach 250 mA - derate the supply accordingly.
Place a JTAG header (TCK, TMS, TDI, TDO, GND, VCC) near the device for in-system programming. The 84-PLCC socket should be a low-profile machined-pin type to ensure reliable JTAG ISP contact. Route TCK with a ground guard trace to avoid JTAG communication errors, and keep JTAG traces short (<50 mm). For high-noise environments, add 10 kohm pull-ups on TMS and TDI to keep the JTAG state machine in a known reset state during power-up.
Assign high-speed clocks to dedicated INPUT/GCLK pins (pins 42-44 in 84-PLCC) to drive the global clock network with minimum skew. Reserve a separate ground plane under the PLCC socket for low-impedance return paths, and route 5.0-V VCCIO with at least 0.5 mm trace width to limit voltage drop. For PCI bus designs, match trace lengths within the 2.5 ns PCI 2.2 spec; the -10 speed grade gives 10 ns tPD, leaving margin for interconnect delay.
Do not apply 3.3-V signals directly to the EPM9320ALC84-10 I/O - it is a 5.0-V-only device and signals above VCCIO + 0.5 V can damage input structures. Use a level shifter or buffer when interfacing to 3.3-V logic. Additionally, the JTAG TCK must not exceed 10 MHz for reliable ISP operation; if faster programming is required, use the parallel ByteBlasterMV or USB-Blaster download cable. Always issue the BYPASS instruction before powering down to avoid spurious JTAG state machine transitions.
コンプライアンス情報
Compliance data not in the verified web data sources. The EPM9320ALC84-10N variant indicates lead-free (Pb-free) reflow compatibility per Intel/Altera naming convention. RoHS and REACH status to be verified against the manufacturer datasheet before new designs.