EPM9320ARI208-10N vs EPM9320ARC208-10 比較
詳細な並列比較: EPM9320ARI208-10N メーカー: Altera および EPM9320ARC208-10 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
Altera
EPM9320ARI208-10N - MAX 9000 CPLD, 320 Macrocells, 208-RQFP | Altera
EPM9320ARI208-10N Obsolete
仕様比較
| パラメータ | EPM9320ARI208-10N | EPM9320ARC208-10 |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | ラストバイ |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $16.20 | $21.40 |
| Family | MAX 9000 | — |
| Product Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Usable Gates | 6,000 | 6,000 |
| Macrocells | 320 | 320 |
| Logic Array Blocks (LABs) | 20 | — |
| Maximum Operating Frequency | 144.9 MHz | — |
| Propagation Delay (tPD) | 10 ns (speed grade -10) | — |
| 電源電圧 | 4.5 V to 5.5 V | 5.0 V |
| 動作温度 | -40 C to +85 C (industrial) | [DATA_NEEDED: operating temperature range] |
| パッケージ | 208-pin RQFP (S-PQFP-G208) | RQFP-208 (Power Quad Flat Pack) |
| 実装タイプ | Surface Mount | Surface Mount |
| Process Technology | CMOS EEPROM | — |
| Programmability | In-system (ISP) via IEEE 1149.1 JTAG | EEPROM, in-system programmable via JTAG |
| Global Dedicated Inputs | 16 | — |
| Architecture | Multiple Array MatriX (MAX) third-generation | — |
| RoHS ステータス | unknown | [DATA_NEEDED: RoHS compliance status] |
| Device Family | — | MAX 9000 |
| Pin-to-Pin Delay (tPD) | — | 10 ns |
| Maximum Frequency | — | 144.9 MHz |
| Logic Blocks (LABs) | — | 16 |
| JTAG Support | — | IEEE Std. 1149.1 compliant |
| Speed/Power Optimization | — | Per-macrocell programmable, 50% power mode available |