K4S641632H-UC75 vs K4S641632K-UC75 比較
詳細な並列比較: K4S641632H-UC75 メーカー: Samsung Electronics および K4S641632K-UC75 メーカー: Samsung Electro-Mechanics。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
Samsung Electronics
K4S641632H-UC75 - 64Mb H-die SDRAM 1M x 16 x 4 Banks | Samsung
K4S641632H-UC75 ObsoleteSamsung Electro-Mechanics
K4S641632K-UC75 - 64Mb SDRAM 4Mx16 3.3V 54-TSOP II | Samsung
K4S641632K-UC75 ✓ 生産中仕様比較
| パラメータ | K4S641632H-UC75 | K4S641632K-UC75 |
|---|---|---|
| ブランド | Samsung Electronics | Samsung Electro-Mechanics |
| カテゴリ | Memory ICs | Memory ICs |
| ライフサイクル状態 | Obsolete | 有効 |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $2.85 | $0.92 |
| Density | 64 Mb (67,108,864 bits) | 64 Mbit (67,108,864 bits) |
| メモリ構成 | 1M x 16 bits x 4 Banks | 4 banks x 1,048,576 words x 16 bits (4Mx16) |
| メモリタイプ | SDRAM (Synchronous DRAM) | Synchronous DRAM (SDR SDRAM) |
| Clock Frequency | 133 MHz | — |
| Supply Voltage (VDD/VDDQ) | 3.3 V | 3.3 V +/- 0.3 V |
| インターフェース | LVCMOS | 16-bit data bus, LVTTL-compatible |
| Max Operating Current | 135 mA | — |
| 動作温度 | 0C to +70C (Commercial) | 0 C to +70 C (Commercial) |
| Package Type | 54-pin TSOP-II | — |
| Lead Finish | Pb-Free (RoHS compliant) | — |
| Bank Architecture | 4 Banks | — |
| Burst Length | 1, 2, 4, 8, Full Page | 1, 2, 4, 8 or full page |
| Burst Type | Sequential or Interleave | — |
| Address Multiplexing | Yes (RAS#, CAS# controlled) | Row: 12 bits, Column: 8 bits |
| Refresh | Auto-Refresh and Self-Refresh | — |
| Process Technology | Samsung high-performance CMOS | Samsung high-performance CMOS |
| Data Width | 16 bits | — |
| Speed Grade | — | UC75 (133 MHz, CAS Latency 3, tCK = 7.5 ns) |
| 最大クロック周波数 | — | 133 MHz |
| CAS Latency (CL) | — | 2 or 3 (programmable) |
| Refresh Cycles | — | 4096 (64 ms refresh interval) |
| Number of Banks | — | 4 |
| パッケージ | — | 54-pin TSOP-II |
| Package Outline | — | 10.16 mm x 22.22 mm, 0.8 mm pitch |
| 実装タイプ | — | Surface Mount (Tape & Reel) |
| RoHS ステータス | — | Compliant |