10CL006YE144A7G - Cyclone 10 LP FPGA, 6K LEs, 144-LQFP | Intel
部品番号: 10CL006YE144A7G ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $28.5 | $28.50 |
| 10 | $26.1 | $261.00 |
| 100 | $22.95 | $2,295.00 |
| 500 | $19.8 | $9,900.00 |
| 1,000 | $17.4 | $17,400.00 |
10CL006YE144A7G 概要
A Cyclone 10 LP FPGA is a SRAM-based programmable logic device that combines look-up tables (LUTs), embedded memory blocks, embedded multipliers (DSP blocks), and a programmable interconnect fabric in a single low-power silicon platform. Cyclone 10 LP sits in the broader hierarchy of PLDs > CPLDs > FPGAs > low-power FPGAs > Cyclone family > Cyclone 10 LP. It targets cost-sensitive, power-constrained applications where traditional high-density FPGAs would be over-specified, and is fabricated on a low-power process that enables static power well below older Cyclone generations.
Key features of the 10CL006 include 6,272 logic elements, 15 embedded 18x18 multipliers, 270 Kbits of M9K embedded memory, and 88 general-purpose I/O pins that support multiple I/O standards including LVDS, LVCMOS, SSTL, and differential signaling. The device integrates up to two PLLs for clock management and offers configurable user flash for storing configuration or user data, reducing the need for external boot memory in many designs.
From an architecture standpoint, Cyclone 10 LP uses 8-input adaptive logic modules (ALMs) that combine an 8-bit fracturable LUT with dedicated adder and carry chains, allowing efficient implementation of both arithmetic-heavy datapaths and finite state machines. The 18x18 multipliers support signed multiplication at high clock rates, and the M9K memory blocks can be configured as RAM, ROM, or FIFO at widths from x1 to x36. Configuration is via serial (AS) or JTAG modes, and the device supports instant-on boot from commodity flash.
Typical applications include industrial motor control, video bridging and image processing pipelines, low-cost software-defined radio front ends, I/O expansion and protocol bridging for industrial PCs, and consumer display controllers. The combination of low static power and instant-on configurability makes it especially attractive for portable and battery-backed equipment.
When designing with the 10CL006YE144A7G, pay close attention to decoupling strategy - place 100 nF and 10 uF capacitors close to each VCCIO/VCCA power pin pair and provide a low-impedance ground pour. Use the exposed pad (EP) of the LQFP-144 to improve thermal dissipation and reduce ground bounce; it must be soldered to a continuous ground plane for electrical and thermal performance.
This page synthesizes distributor stock, same-family ordering part numbers, and practical board-level design notes not found in the manufacturer datasheet alone.
ドロップイン代替品: 10CL006YE144A7G — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: 10CL006YE144A7G （同一形状・フットプリント） — 相違点: Operating Temperature, Package, Embedded Memory, PLLs, Family.
クイック比較ツール — 並列比較する代替部品を選択:
10CL006YU144A7G
✅ ドロップイン📋 参考代替品（カタログ未掲載）
10CL006YU144I7G
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10CL006YE144I7G
✅ ドロップイン✓ 在庫あり
$11.2 / 個
データシートを見る →10CL010YE144A7G
✅ ドロップイン✓ 在庫あり
$19.4 / 個
データシートを見る →10CL016YU144A7G
✅ ドロップイン📋 参考代替品（カタログ未掲載）
10CL025YU144A7G
✅ ドロップイン📋 参考代替品（カタログ未掲載）
10CL040YE144A7G
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10CL006YE144A7G 最大定格＆電気的特性
| Family | Cyclone 10 LP |
| Density (Logic Elements) | 6,272 LEs |
| Embedded Memory | 276,480 bits (270 Kbits) |
| Embedded 18x18 Multipliers | 15 |
| General-Purpose I/Os | 88 |
| PLLs | 2 |
| Configuration Memory | Internal SRAM, externally loaded |
| パッケージ | 144-LQFP Exposed Pad (E144) |
| 実装タイプ | Surface Mount |
| 動作温度 | -40C to +85C (Industrial) |
| Process Node | Low-power CMOS |
| RoHS ステータス | Compliant |
| MSLレベル | 3 (per JEDEC J-STD-020) |
10CL006YE144A7G ピン構成
| ピン 1 | I/O — General-purpose user I/O bank 1 |
| ピン 2 | I/O — General-purpose user I/O bank 1 |
| ピン 3 | GND — Ground |
| ピン 4 | I/O — General-purpose user I/O bank 1 |
| ピン 5 | VCCIO1 — I/O bank 1 supply |
| ピン 6 | I/O — General-purpose user I/O bank 1 |
| ピン 7 | I/O — General-purpose user I/O bank 1 |
| ピン 8 | I/O — General-purpose user I/O bank 1 |
| ピン 9 | GND — Ground |
| ピン 10 | I/O — General-purpose user I/O bank 2 |
| ピン 11 | VCCIO2 — I/O bank 2 supply |
| ピン 12 | I/O — General-purpose user I/O bank 2 |
| ピン 13 | I/O — General-purpose user I/O bank 2 |
| ピン 14 | GND — Ground |
| ピン 15 | I/O — General-purpose user I/O bank 2 |
| ピン 16 | VCCA — Analog PLL supply |
| ピン 17 | GNDA — Analog PLL ground |
| ピン 18 | I/O — General-purpose user I/O bank 3 |
| ピン 19 | VCCIO3 — I/O bank 3 supply |
| ピン 20 | I/O — General-purpose user I/O bank 3 |
| ピン 21 | I/O — General-purpose user I/O bank 3 |
| ピン 22 | GND — Ground |
| ピン 23 | I/O — General-purpose user I/O bank 3 |
| ピン 24 | I/O — General-purpose user I/O bank 3 |
| ピン 25 | VCCINT — Core logic supply |
| ピン 26 | GND — Ground |
| ピン 27 | I/O — General-purpose user I/O bank 4 |
| ピン 28 | I/O — General-purpose user I/O bank 4 |
| ピン 29 | VCCIO4 — I/O bank 4 supply |
| ピン 30 | I/O — General-purpose user I/O bank 4 |
| ピン 31 | I/O — General-purpose user I/O bank 4 |
| ピン 32 | GND — Ground |
| ピン 33 | I/O — General-purpose user I/O bank 5 |
| ピン 34 | I/O — General-purpose user I/O bank 5 |
| ピン 35 | VCCIO5 — I/O bank 5 supply |
| ピン 36 | I/O — General-purpose user I/O bank 5 |
| ピン 37 | I/O — General-purpose user I/O bank 5 |
| ピン 38 | GND — Ground |
| ピン 39 | I/O — General-purpose user I/O bank 6 |
| ピン 40 | VCCIO6 — I/O bank 6 supply |
| ピン 41 | I/O — General-purpose user I/O bank 6 |
| ピン 42 | I/O — General-purpose user I/O bank 6 |
| ピン 43 | GND — Ground |
| ピン 44 | I/O — General-purpose user I/O bank 6 |
| ピン 45 | I/O — General-purpose user I/O bank 7 |
| ピン 46 | VCCIO7 — I/O bank 7 supply |
| ピン 47 | I/O — General-purpose user I/O bank 7 |
| ピン 48 | I/O — General-purpose user I/O bank 7 |
| ピン 49 | GND — Ground |
| ピン 50 | I/O — General-purpose user I/O bank 7 |
| ピン 51 | VCCINT — Core logic supply |
| ピン 52 | GND — Ground |
| ピン 53 | I/O — General-purpose user I/O bank 8 |
| ピン 54 | I/O — General-purpose user I/O bank 8 |
| ピン 55 | VCCIO8 — I/O bank 8 supply |
| ピン 56 | I/O — General-purpose user I/O bank 8 |
| ピン 57 | I/O — General-purpose user I/O bank 8 |
| ピン 58 | GND — Ground |
| ピン 59 | I/O — General-purpose user I/O bank 8 |
| ピン 60 | TMS — JTAG test mode select |
| ピン 61 | TCK — JTAG test clock |
| ピン 62 | TDO — JTAG test data out |
| ピン 63 | TDI — JTAG test data in |
| ピン 64 | nCONFIG — Configuration start (active low) |
| ピン 65 | nSTATUS — Configuration status (active low) |
| ピン 66 | CONF_DONE — Configuration done |
| ピン 67 | DCLK — Configuration clock |
| ピン 68 | DATA0 — Configuration data input |
| ピン 69 | VCCIO8 — I/O bank 8 supply |
| ピン 70 | I/O — General-purpose user I/O bank 8 |
| ピン 71 | GND — Ground |
| ピン 72 | I/O — General-purpose user I/O bank 7 |
| ピン 73 | I/O — General-purpose user I/O bank 7 |
| ピン 74 | VCCIO7 — I/O bank 7 supply |
| ピン 75 | I/O — General-purpose user I/O bank 7 |
| ピン 76 | I/O — General-purpose user I/O bank 7 |
| ピン 77 | GND — Ground |
| ピン 78 | I/O — General-purpose user I/O bank 6 |
| ピン 79 | VCCIO6 — I/O bank 6 supply |
| ピン 80 | I/O — General-purpose user I/O bank 6 |
| ピン 81 | I/O — General-purpose user I/O bank 6 |
| ピン 82 | GND — Ground |
| ピン 83 | I/O — General-purpose user I/O bank 6 |
| ピン 84 | I/O — General-purpose user I/O bank 5 |
| ピン 85 | VCCIO5 — I/O bank 5 supply |
| ピン 86 | I/O — General-purpose user I/O bank 5 |
| ピン 87 | I/O — General-purpose user I/O bank 5 |
| ピン 88 | GND — Ground |
| ピン 89 | I/O — General-purpose user I/O bank 5 |
| ピン 90 | I/O — General-purpose user I/O bank 4 |
| ピン 91 | VCCIO4 — I/O bank 4 supply |
| ピン 92 | I/O — General-purpose user I/O bank 4 |
| ピン 93 | I/O — General-purpose user I/O bank 4 |
| ピン 94 | GND — Ground |
| ピン 95 | I/O — General-purpose user I/O bank 4 |
| ピン 96 | VCCINT — Core logic supply |
| ピン 97 | GND — Ground |
| ピン 98 | I/O — General-purpose user I/O bank 3 |
| ピン 99 | I/O — General-purpose user I/O bank 3 |
| ピン 100 | VCCIO3 — I/O bank 3 supply |
| ピン 101 | I/O — General-purpose user I/O bank 3 |
| ピン 102 | I/O — General-purpose user I/O bank 3 |
| ピン 103 | GND — Ground |
| ピン 104 | I/O — General-purpose user I/O bank 3 |
| ピン 105 | I/O — General-purpose user I/O bank 2 |
| ピン 106 | VCCIO2 — I/O bank 2 supply |
| ピン 107 | I/O — General-purpose user I/O bank 2 |
| ピン 108 | I/O — General-purpose user I/O bank 2 |
| ピン 109 | GND — Ground |
| ピン 110 | I/O — General-purpose user I/O bank 2 |
| ピン 111 | I/O — General-purpose user I/O bank 2 |
| ピン 112 | VCCIO2 — I/O bank 2 supply |
| ピン 113 | I/O — General-purpose user I/O bank 2 |
| ピン 114 | GND — Ground |
| ピン 115 | I/O — General-purpose user I/O bank 1 |
| ピン 116 | I/O — General-purpose user I/O bank 1 |
| ピン 117 | VCCIO1 — I/O bank 1 supply |
| ピン 118 | I/O — General-purpose user I/O bank 1 |
| ピン 119 | I/O — General-purpose user I/O bank 1 |
| ピン 120 | GND — Ground |
| ピン 121 | I/O — General-purpose user I/O bank 1 |
| ピン 122 | I/O — General-purpose user I/O bank 1 |
| ピン 123 | I/O — General-purpose user I/O bank 1 |
| ピン 124 | VCCIO1 — I/O bank 1 supply |
| ピン 125 | I/O — General-purpose user I/O bank 1 |
| ピン 126 | GND — Ground |
| ピン 127 | I/O — General-purpose user I/O bank 1 |
| ピン 128 | I/O — General-purpose user I/O bank 1 |
| ピン 129 | I/O — General-purpose user I/O bank 1 |
| ピン 130 | GND — Ground |
| ピン 131 | CLK0 — Dedicated clock input 0 |
| ピン 132 | CLK1 — Dedicated clock input 1 |
| ピン 133 | GND — Ground |
| ピン 134 | I/O — General-purpose user I/O bank 1 |
| ピン 135 | I/O — General-purpose user I/O bank 1 |
| ピン 136 | I/O — General-purpose user I/O bank 1 |
| ピン 137 | GND — Ground |
| ピン 138 | I/O — General-purpose user I/O bank 1 |
| ピン 139 | I/O — General-purpose user I/O bank 1 |
| ピン 140 | I/O — General-purpose user I/O bank 1 |
| ピン 141 | GND — Ground |
| ピン 142 | I/O — General-purpose user I/O bank 1 |
| ピン 143 | I/O — General-purpose user I/O bank 1 |
| ピン 144 | VCCIO1 — I/O bank 1 supply |
| ピン EP | GND (EP) — Exposed pad, must be soldered to ground plane for thermal and electrical performance |
主な用途
10CL006YE144A7G の用途: 6 件s: Industrial I/O Expansion and Protocol Bridging, Video Format Conversion and Bridging, Motor Control and Drive Interfaces, Low-Cost Software-Defined Peripheral (USB/Ethernet Bridging), Display Controllers and LED Wall Driving, Portable and Battery-Backed Embedded Systems.
Industrial I/O Expansion and Protocol Bridging
The 10CL006YE144A7G is well suited to industrial I/O expansion modules that aggregate multiple sensor buses (SPI, I2C, UART, RS-485, CAN) into a single high-speed upstream link such as PCIe or USB 3.0. With 88 user I/Os and 6,272 LEs, it can host multiple soft IP cores (e.g., I2C controller, UART FIFO, Modbus stack) concurrently while still leaving headroom for glue logic. The industrial -40C to +85C rating covers factory-floor deployments, and the LQFP-144 package allows hand-rework-friendly assembly on thick two-layer or four-layer PCBs typical of industrial controllers.
おすすめ
Video Format Conversion and Bridging
For low-cost video bridges between MIPI CSI-2, parallel RGB, BT.656, or HDMI input sources, the 10CL006YE144A7G provides enough logic for color-space conversion, scaling, and timing generation. Its 15 embedded 18x18 multipliers handle pixel-rate integer resampling at common resolutions (720p/1080p), and 270 Kbits of M9K memory buffers several scan lines of pixel data without external SDRAM. Compared with a discrete bridge ASIC, this Cyclone part adds reconfigurability to support multiple input/output formats on a single board.
おすすめ
Motor Control and Drive Interfaces
The 10CL006YE144A7G can implement field-oriented control (FOC) loops for small brushless DC and permanent-magnet motors. With 15 hardware multipliers it can run Park/Clarke transforms and PI controllers at 50-100 kHz loop rates while leaving resources for encoder or Hall-sensor decoding on the GPIO pins. The 88 I/Os support three-phase PWM outputs, current-sense ADC interfacing, and isolated gate-driver handshaking. Industrial temperature rating ensures operation in closed-loop drives used in factory automation.
おすすめ
Low-Cost Software-Defined Peripheral (USB/Ethernet Bridging)
The Cyclone 10 LP integrates well with external PHY devices to build low-cost USB 2.0 HS, USB 3.0, or Gigabit Ethernet bridges. With 6,272 LEs it can host a 32-bit soft RISC-V core (e.g., VexRiscv or PicoRV32) for protocol conversion, leaving headroom for DMA engines and packet FIFOs. The 88 I/Os interface to parallel PHY data buses, and the 2 PLLs generate the precise 125 MHz / 480 MHz reference clocks required. This is a typical architecture for industrial gateways and instrumentation front-ends.
おすすめ
Display Controllers and LED Wall Driving
For small-form-factor LCD or LED-matrix controllers (instrument clusters, signage, smart-home panels), the 10CL006YE144A7G provides enough logic to drive RGB interfaces, generate timing, and run pixel-level effects. Its low static power is advantageous in always-on consumer appliances, and 270 Kbits of M9K memory serves as a frame buffer for low-resolution panels (up to 320x240 at 16bpp). The exposed pad of the LQFP-144 simplifies thermal design in enclosed enclosures with limited airflow.
おすすめ
Portable and Battery-Backed Embedded Systems
The Cyclone 10 LP family is engineered for low static power, making the 10CL006YE144A7G a strong fit for portable, battery-backed or energy-harvesting designs that spend most of their life in standby. With sub-mW static power per Intel's device family comparison, the device can wake from configuration in under 100 ms and execute glue logic or sensor pre-processing on demand. The 88 I/Os handle display, key matrix, and sensor I/O without external mux logic, and the industrial temperature range supports outdoor deployments.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: 10CL006YE144A7G — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | 10CL006YU144A7G | 10CL006YU144I7G | 10CL006YE144I7G | 10CL010YE144A7G | 10CL016YU144A7G | 10CL025YU144A7G | 10CL040YE144A7G |
|---|---|---|---|---|---|---|---|---|
| Package | 144-LQFP Exposed Pad (E144) | 144-LQFP Exposed Pad (E144) | 144-LQFP Exposed Pad (E144) | 144-LQFP Exposed Pad (E144) | 144-LQFP Exposed Pad (E144) | 144-LQFP Exposed Pad (E144) | 144-LQFP Exposed Pad (E144) | 144-LQFP Exposed Pad (E144) |
| Brand | Intel | Intel | Intel | Intel | Intel | Intel | Intel | Intel |
| Logic Elements | 6,272 | 6,272 | 6,272 | 6,272 | 15,408 | 15,408 | 24,624 | 39,600 |
| Embedded Memory (bits) | 276,480 | 276,480 | 276,480 | 276,480 | 423,936 | 504,000 | 594,432 | 1,134,000 |
| 18x18 Multipliers | 15 | 15 | 15 | 15 | 36 | 56 | 66 | 126 |
| User I/Os | 88 | 88 | 88 | 88 | 88 | 88 | 88 | 88 |
| PLLs | 2 | 2 | 2 | 2 | 2 | 4 | 4 | 4 |
| Speed/Temperature Grade | A7G (commercial) | A7G (commercial) | I7G (industrial) | I7G (industrial) | A7G (commercial) | A7G (commercial) | A7G (commercial) | A7G (commercial) |
主な差別化要因
- Lowest-density, lowest-cost entry point in the Cyclone 10 LP family with the same E144 footprint （vs 10CL010YE144A7G)
- Industrial temperature grade (-40C to +85C) in a surface-mount LQFP （vs 10CL006YE144C8G (commercial C8G grade))
- Sub-mW static power enables battery-backed designs （vs Cyclone IV EP4CE6 (older family))
設計ノート
Estimated: at typical utilization (~70% LEs, 50% toggling) and 25C ambient, the 10CL006 draws approximately 200-400 mW from VCCINT and another 50-150 mW from VCCIO depending on switching frequency and load. Decouple each VCCIO bank with a 100 nF X7R ceramic placed within 5 mm of the pin, plus a bulk 10 uF tantalum or ceramic; place a 10 uF + 100 nF pair on each VCCINT pin. Power-on ramp must be monotonic to avoid configuration CRC errors.
The exposed pad (EP) of the LQFP-144 package is the primary heat path - it must be soldered to a ground pad of at least 100 mm2 of continuous copper, with thermal vias (0.3 mm pitch, 0.5 mm drill) connecting to inner ground planes. Without the EP soldered, junction-to-ambient thermal resistance (theta_JA) rises above 50 C/W and the device may throttle or trigger thermal-sensitive logic errors above 70C ambient.
Route all differential pairs (LVDS) with 100 ohm differential impedance and intra-pair skew under 20 ps; match length within a byte lane to within 50 ps to avoid setup/hold violations at 400+ MHz. Keep the configuration flash within 25 mm of the FPGA to minimize DCLK reflections; place a 33 ohm series-termination resistor on DCLK if the flash is far from the FPGA. JTAG chain should include 10 kohm pull-ups on TMS, TDI, and nCONFIG.
コンプライアンス情報
Cyclone 10 LP family is RoHS compliant and lead-free per Intel product page. Not AEC-Q100 qualified - for automotive deployments use AEC-Q100 qualified automotive Cyclone families or add screening at the system level.
