10CL006YE144A7G - Cyclone 10 LP FPGA, 6K LEs, 144-LQFP | Intel
MPN: 10CL006YE144A7G β Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $28.5 | $28.50 |
| 10 | $26.1 | $261.00 |
| 100 | $22.95 | $2,295.00 |
| 500 | $19.8 | $9,900.00 |
| 1,000 | $17.4 | $17,400.00 |
Drop-in alternatives for 10CL006YE144A7G β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
10CL006YU144A7G
β Drop-Inπ Reference alternative (not in catalog)
10CL006YU144I7G
β Drop-Inπ Reference alternative (not in catalog)
10CL006YE144I7G
β Drop-Inβ In Stock
$11.2 / Unit
View Datasheet β10CL010YE144A7G
β Drop-Inβ In Stock
$19.4 / Unit
View Datasheet β10CL016YU144A7G
β Drop-Inπ Reference alternative (not in catalog)
10CL025YU144A7G
β Drop-Inπ Reference alternative (not in catalog)
10CL040YE144A7G
β Drop-Inπ Reference alternative (not in catalog)
10CL006YE144A7G Maximum Ratings & Electrical Characteristics
| Family | Cyclone 10 LP |
| Density (Logic Elements) | 6,272 LEs |
| Embedded Memory | 276,480 bits (270 Kbits) |
| Embedded 18x18 Multipliers | 15 |
| General-Purpose I/Os | 88 |
| PLLs | 2 |
| Configuration Memory | Internal SRAM, externally loaded |
| Package | 144-LQFP Exposed Pad (E144) |
| Mounting Type | Surface Mount |
| Operating Temperature | -40C to +85C (Industrial) |
| Process Node | Low-power CMOS |
| RoHS Status | Compliant |
| MSL Level | 3 (per JEDEC J-STD-020) |
10CL006YE144A7G Pin Configuration
| Pin 1 | I/O β General-purpose user I/O bank 1 |
| Pin 2 | I/O β General-purpose user I/O bank 1 |
| Pin 3 | GND β Ground |
| Pin 4 | I/O β General-purpose user I/O bank 1 |
| Pin 5 | VCCIO1 β I/O bank 1 supply |
| Pin 6 | I/O β General-purpose user I/O bank 1 |
| Pin 7 | I/O β General-purpose user I/O bank 1 |
| Pin 8 | I/O β General-purpose user I/O bank 1 |
| Pin 9 | GND β Ground |
| Pin 10 | I/O β General-purpose user I/O bank 2 |
| Pin 11 | VCCIO2 β I/O bank 2 supply |
| Pin 12 | I/O β General-purpose user I/O bank 2 |
| Pin 13 | I/O β General-purpose user I/O bank 2 |
| Pin 14 | GND β Ground |
| Pin 15 | I/O β General-purpose user I/O bank 2 |
| Pin 16 | VCCA β Analog PLL supply |
| Pin 17 | GNDA β Analog PLL ground |
| Pin 18 | I/O β General-purpose user I/O bank 3 |
| Pin 19 | VCCIO3 β I/O bank 3 supply |
| Pin 20 | I/O β General-purpose user I/O bank 3 |
| Pin 21 | I/O β General-purpose user I/O bank 3 |
| Pin 22 | GND β Ground |
| Pin 23 | I/O β General-purpose user I/O bank 3 |
| Pin 24 | I/O β General-purpose user I/O bank 3 |
| Pin 25 | VCCINT β Core logic supply |
| Pin 26 | GND β Ground |
| Pin 27 | I/O β General-purpose user I/O bank 4 |
| Pin 28 | I/O β General-purpose user I/O bank 4 |
| Pin 29 | VCCIO4 β I/O bank 4 supply |
| Pin 30 | I/O β General-purpose user I/O bank 4 |
| Pin 31 | I/O β General-purpose user I/O bank 4 |
| Pin 32 | GND β Ground |
| Pin 33 | I/O β General-purpose user I/O bank 5 |
| Pin 34 | I/O β General-purpose user I/O bank 5 |
| Pin 35 | VCCIO5 β I/O bank 5 supply |
| Pin 36 | I/O β General-purpose user I/O bank 5 |
| Pin 37 | I/O β General-purpose user I/O bank 5 |
| Pin 38 | GND β Ground |
| Pin 39 | I/O β General-purpose user I/O bank 6 |
| Pin 40 | VCCIO6 β I/O bank 6 supply |
| Pin 41 | I/O β General-purpose user I/O bank 6 |
| Pin 42 | I/O β General-purpose user I/O bank 6 |
| Pin 43 | GND β Ground |
| Pin 44 | I/O β General-purpose user I/O bank 6 |
| Pin 45 | I/O β General-purpose user I/O bank 7 |
| Pin 46 | VCCIO7 β I/O bank 7 supply |
| Pin 47 | I/O β General-purpose user I/O bank 7 |
| Pin 48 | I/O β General-purpose user I/O bank 7 |
| Pin 49 | GND β Ground |
| Pin 50 | I/O β General-purpose user I/O bank 7 |
| Pin 51 | VCCINT β Core logic supply |
| Pin 52 | GND β Ground |
| Pin 53 | I/O β General-purpose user I/O bank 8 |
| Pin 54 | I/O β General-purpose user I/O bank 8 |
| Pin 55 | VCCIO8 β I/O bank 8 supply |
| Pin 56 | I/O β General-purpose user I/O bank 8 |
| Pin 57 | I/O β General-purpose user I/O bank 8 |
| Pin 58 | GND β Ground |
| Pin 59 | I/O β General-purpose user I/O bank 8 |
| Pin 60 | TMS β JTAG test mode select |
| Pin 61 | TCK β JTAG test clock |
| Pin 62 | TDO β JTAG test data out |
| Pin 63 | TDI β JTAG test data in |
| Pin 64 | nCONFIG β Configuration start (active low) |
| Pin 65 | nSTATUS β Configuration status (active low) |
| Pin 66 | CONF_DONE β Configuration done |
| Pin 67 | DCLK β Configuration clock |
| Pin 68 | DATA0 β Configuration data input |
| Pin 69 | VCCIO8 β I/O bank 8 supply |
| Pin 70 | I/O β General-purpose user I/O bank 8 |
| Pin 71 | GND β Ground |
| Pin 72 | I/O β General-purpose user I/O bank 7 |
| Pin 73 | I/O β General-purpose user I/O bank 7 |
| Pin 74 | VCCIO7 β I/O bank 7 supply |
| Pin 75 | I/O β General-purpose user I/O bank 7 |
| Pin 76 | I/O β General-purpose user I/O bank 7 |
| Pin 77 | GND β Ground |
| Pin 78 | I/O β General-purpose user I/O bank 6 |
| Pin 79 | VCCIO6 β I/O bank 6 supply |
| Pin 80 | I/O β General-purpose user I/O bank 6 |
| Pin 81 | I/O β General-purpose user I/O bank 6 |
| Pin 82 | GND β Ground |
| Pin 83 | I/O β General-purpose user I/O bank 6 |
| Pin 84 | I/O β General-purpose user I/O bank 5 |
| Pin 85 | VCCIO5 β I/O bank 5 supply |
| Pin 86 | I/O β General-purpose user I/O bank 5 |
| Pin 87 | I/O β General-purpose user I/O bank 5 |
| Pin 88 | GND β Ground |
| Pin 89 | I/O β General-purpose user I/O bank 5 |
| Pin 90 | I/O β General-purpose user I/O bank 4 |
| Pin 91 | VCCIO4 β I/O bank 4 supply |
| Pin 92 | I/O β General-purpose user I/O bank 4 |
| Pin 93 | I/O β General-purpose user I/O bank 4 |
| Pin 94 | GND β Ground |
| Pin 95 | I/O β General-purpose user I/O bank 4 |
| Pin 96 | VCCINT β Core logic supply |
| Pin 97 | GND β Ground |
| Pin 98 | I/O β General-purpose user I/O bank 3 |
| Pin 99 | I/O β General-purpose user I/O bank 3 |
| Pin 100 | VCCIO3 β I/O bank 3 supply |
| Pin 101 | I/O β General-purpose user I/O bank 3 |
| Pin 102 | I/O β General-purpose user I/O bank 3 |
| Pin 103 | GND β Ground |
| Pin 104 | I/O β General-purpose user I/O bank 3 |
| Pin 105 | I/O β General-purpose user I/O bank 2 |
| Pin 106 | VCCIO2 β I/O bank 2 supply |
| Pin 107 | I/O β General-purpose user I/O bank 2 |
| Pin 108 | I/O β General-purpose user I/O bank 2 |
| Pin 109 | GND β Ground |
| Pin 110 | I/O β General-purpose user I/O bank 2 |
| Pin 111 | I/O β General-purpose user I/O bank 2 |
| Pin 112 | VCCIO2 β I/O bank 2 supply |
| Pin 113 | I/O β General-purpose user I/O bank 2 |
| Pin 114 | GND β Ground |
| Pin 115 | I/O β General-purpose user I/O bank 1 |
| Pin 116 | I/O β General-purpose user I/O bank 1 |
| Pin 117 | VCCIO1 β I/O bank 1 supply |
| Pin 118 | I/O β General-purpose user I/O bank 1 |
| Pin 119 | I/O β General-purpose user I/O bank 1 |
| Pin 120 | GND β Ground |
| Pin 121 | I/O β General-purpose user I/O bank 1 |
| Pin 122 | I/O β General-purpose user I/O bank 1 |
| Pin 123 | I/O β General-purpose user I/O bank 1 |
| Pin 124 | VCCIO1 β I/O bank 1 supply |
| Pin 125 | I/O β General-purpose user I/O bank 1 |
| Pin 126 | GND β Ground |
| Pin 127 | I/O β General-purpose user I/O bank 1 |
| Pin 128 | I/O β General-purpose user I/O bank 1 |
| Pin 129 | I/O β General-purpose user I/O bank 1 |
| Pin 130 | GND β Ground |
| Pin 131 | CLK0 β Dedicated clock input 0 |
| Pin 132 | CLK1 β Dedicated clock input 1 |
| Pin 133 | GND β Ground |
| Pin 134 | I/O β General-purpose user I/O bank 1 |
| Pin 135 | I/O β General-purpose user I/O bank 1 |
| Pin 136 | I/O β General-purpose user I/O bank 1 |
| Pin 137 | GND β Ground |
| Pin 138 | I/O β General-purpose user I/O bank 1 |
| Pin 139 | I/O β General-purpose user I/O bank 1 |
| Pin 140 | I/O β General-purpose user I/O bank 1 |
| Pin 141 | GND β Ground |
| Pin 142 | I/O β General-purpose user I/O bank 1 |
| Pin 143 | I/O β General-purpose user I/O bank 1 |
| Pin 144 | VCCIO1 β I/O bank 1 supply |
| Pin EP | GND (EP) β Exposed pad, must be soldered to ground plane for thermal and electrical performance |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
10CL006YE144A7G is suitable for 6 applications: Industrial I/O Expansion and Protocol Bridging, Video Format Conversion and Bridging, Motor Control and Drive Interfaces, Low-Cost Software-Defined Peripheral (USB/Ethernet Bridging), Display Controllers and LED Wall Driving, Portable and Battery-Backed Embedded Systems.
Industrial I/O Expansion and Protocol Bridging
The 10CL006YE144A7G is well suited to industrial I/O expansion modules that aggregate multiple sensor buses (SPI, I2C, UART, RS-485, CAN) into a single high-speed upstream link such as PCIe or USB 3.0. With 88 user I/Os and 6,272 LEs, it can host multiple soft IP cores (e.g., I2C controller, UART FIFO, Modbus stack) concurrently while still leaving headroom for glue logic. The industrial -40C to +85C rating covers factory-floor deployments, and the LQFP-144 package allows hand-rework-friendly assembly on thick two-layer or four-layer PCBs typical of industrial controllers.
Recommended
Video Format Conversion and Bridging
For low-cost video bridges between MIPI CSI-2, parallel RGB, BT.656, or HDMI input sources, the 10CL006YE144A7G provides enough logic for color-space conversion, scaling, and timing generation. Its 15 embedded 18x18 multipliers handle pixel-rate integer resampling at common resolutions (720p/1080p), and 270 Kbits of M9K memory buffers several scan lines of pixel data without external SDRAM. Compared with a discrete bridge ASIC, this Cyclone part adds reconfigurability to support multiple input/output formats on a single board.
Recommended
Motor Control and Drive Interfaces
The 10CL006YE144A7G can implement field-oriented control (FOC) loops for small brushless DC and permanent-magnet motors. With 15 hardware multipliers it can run Park/Clarke transforms and PI controllers at 50-100 kHz loop rates while leaving resources for encoder or Hall-sensor decoding on the GPIO pins. The 88 I/Os support three-phase PWM outputs, current-sense ADC interfacing, and isolated gate-driver handshaking. Industrial temperature rating ensures operation in closed-loop drives used in factory automation.
Recommended
Low-Cost Software-Defined Peripheral (USB/Ethernet Bridging)
The Cyclone 10 LP integrates well with external PHY devices to build low-cost USB 2.0 HS, USB 3.0, or Gigabit Ethernet bridges. With 6,272 LEs it can host a 32-bit soft RISC-V core (e.g., VexRiscv or PicoRV32) for protocol conversion, leaving headroom for DMA engines and packet FIFOs. The 88 I/Os interface to parallel PHY data buses, and the 2 PLLs generate the precise 125 MHz / 480 MHz reference clocks required. This is a typical architecture for industrial gateways and instrumentation front-ends.
Recommended
Display Controllers and LED Wall Driving
For small-form-factor LCD or LED-matrix controllers (instrument clusters, signage, smart-home panels), the 10CL006YE144A7G provides enough logic to drive RGB interfaces, generate timing, and run pixel-level effects. Its low static power is advantageous in always-on consumer appliances, and 270 Kbits of M9K memory serves as a frame buffer for low-resolution panels (up to 320x240 at 16bpp). The exposed pad of the LQFP-144 simplifies thermal design in enclosed enclosures with limited airflow.
Recommended
Portable and Battery-Backed Embedded Systems
The Cyclone 10 LP family is engineered for low static power, making the 10CL006YE144A7G a strong fit for portable, battery-backed or energy-harvesting designs that spend most of their life in standby. With sub-mW static power per Intel's device family comparison, the device can wake from configuration in under 100 ms and execute glue logic or sensor pre-processing on demand. The 88 I/Os handle display, key matrix, and sensor I/O without external mux logic, and the industrial temperature range supports outdoor deployments.
Recommended
Recommended Products Summary
Engineering reference data for 10CL006YE144A7G β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | 10CL006YU144A7G | 10CL006YU144I7G | 10CL006YE144I7G | 10CL010YE144A7G | 10CL016YU144A7G | 10CL025YU144A7G | 10CL040YE144A7G |
|---|---|---|---|---|---|---|---|---|
| Package | 144-LQFP Exposed Pad (E144) | 144-LQFP Exposed Pad (E144) | 144-LQFP Exposed Pad (E144) | 144-LQFP Exposed Pad (E144) | 144-LQFP Exposed Pad (E144) | 144-LQFP Exposed Pad (E144) | 144-LQFP Exposed Pad (E144) | 144-LQFP Exposed Pad (E144) |
| Brand | Intel | Intel | Intel | Intel | Intel | Intel | Intel | Intel |
| Logic Elements | 6,272 | 6,272 | 6,272 | 6,272 | 15,408 | 15,408 | 24,624 | 39,600 |
| Embedded Memory (bits) | 276,480 | 276,480 | 276,480 | 276,480 | 423,936 | 504,000 | 594,432 | 1,134,000 |
| 18x18 Multipliers | 15 | 15 | 15 | 15 | 36 | 56 | 66 | 126 |
| User I/Os | 88 | 88 | 88 | 88 | 88 | 88 | 88 | 88 |
| PLLs | 2 | 2 | 2 | 2 | 2 | 4 | 4 | 4 |
| Speed/Temperature Grade | A7G (commercial) | A7G (commercial) | I7G (industrial) | I7G (industrial) | A7G (commercial) | A7G (commercial) | A7G (commercial) | A7G (commercial) |
| Approx. Unit Price @ qty 100 (USD) | 22.95 | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] |
Key Differentiators
- Lowest-density, lowest-cost entry point in the Cyclone 10 LP family with the same E144 footprint (vs 10CL010YE144A7G)
- Industrial temperature grade (-40C to +85C) in a surface-mount LQFP (vs 10CL006YE144C8G (commercial C8G grade))
- Sub-mW static power enables battery-backed designs (vs Cyclone IV EP4CE6 (older family))
Design Notes
Estimated: at typical utilization (~70% LEs, 50% toggling) and 25C ambient, the 10CL006 draws approximately 200-400 mW from VCCINT and another 50-150 mW from VCCIO depending on switching frequency and load. Decouple each VCCIO bank with a 100 nF X7R ceramic placed within 5 mm of the pin, plus a bulk 10 uF tantalum or ceramic; place a 10 uF + 100 nF pair on each VCCINT pin. Power-on ramp must be monotonic to avoid configuration CRC errors.
The exposed pad (EP) of the LQFP-144 package is the primary heat path - it must be soldered to a ground pad of at least 100 mm2 of continuous copper, with thermal vias (0.3 mm pitch, 0.5 mm drill) connecting to inner ground planes. Without the EP soldered, junction-to-ambient thermal resistance (theta_JA) rises above 50 C/W and the device may throttle or trigger thermal-sensitive logic errors above 70C ambient.
Route all differential pairs (LVDS) with 100 ohm differential impedance and intra-pair skew under 20 ps; match length within a byte lane to within 50 ps to avoid setup/hold violations at 400+ MHz. Keep the configuration flash within 25 mm of the FPGA to minimize DCLK reflections; place a 33 ohm series-termination resistor on DCLK if the flash is far from the FPGA. JTAG chain should include 10 kohm pull-ups on TMS, TDI, and nCONFIG.
Compliance Information
Cyclone 10 LP family is RoHS compliant and lead-free per Intel product page. Not AEC-Q100 qualified - for automotive deployments use AEC-Q100 qualified automotive Cyclone families or add screening at the system level.
