10CX105YF672E5G - Cyclone 10 GX FPGA 104K LE | Intel | 672-FCBGA
部品番号: 10CX105YF672E5G ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $425 | $425.00 |
| 10 | $395 | $3,950.00 |
| 100 | $360 | $36,000.00 |
| 250 | $335 | $83,750.00 |
| 500 | $310 | $155,000.00 |
10CX105YF672E5G 概要
An FPGA (Field-Programmable Gate Array) is a semiconductor device whose digital logic fabric, memory blocks, and I/O cells can be reconfigured after manufacture, sitting in the hierarchy: logic cell -> logic array block (LAB) -> FPGA -> programmable logic device (PLD) -> integrated circuit. The Cyclone 10 GX family targets cost- and power-sensitive applications that still need transceivers and DSP blocks for video, industrial, and wireless bridging.
Key features include 0.9 V core operation, six PLLs/DLLs for clock management, dedicated 18x19 multipliers for DSP, embedded SRAM blocks totaling 7,640 Kbit, and JTAG-based configuration via SRAM. The device family is known for low static and dynamic power relative to other 20 nm FPGAs and offers hardened memory controllers and PCIe Gen2 hard IP.
Technical depth comes from the 20 nm TSMC process, an adaptive logic module (ALM) architecture, and hardened transceiver blocks that offload high-speed serial I/O from soft logic. With 382 block RAM instances, designers can implement wide FIFOs, packet buffers, and on-chip frame storage without burning logic resources.
Typical applications include industrial machine vision, video bridging and protocol conversion, low-cost wireless backhaul, motor and motion control, and IoT edge aggregation. Its combination of transceivers and DSP suits parallel processing pipelines.
When designing with this FPGA, plan power sequencing for the 0.9 V core and 1.8/2.5/3.3 V I/O banks separately, and use the Intel Quartus Prime toolchain for synthesis, place-and-route, and timing closure on Cyclone 10 GX.
This page synthesizes distributor pricing, drop-in alternative MPNs from the Cyclone 10 GX family, and practical PCB thermal and signal-integrity guidance not consolidated in the manufacturer datasheet.
ドロップイン代替品: 10CX105YF672E5G — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: 10CX105YF672E5G （同一形状・フットプリント） — 相違点: Package, Embedded Memory, Operating Temperature, Speed Grade, Logic Elements.
クイック比較ツール — 並列比較する代替部品を選択:
10CX105YF672I6G
✅ ドロップイン✓ 在庫あり
$338 / 個
データシートを見る →10CX105YF672E6G
✅ ドロップイン✓ 在庫あり
$100.547 / 個
データシートを見る →10CX105YF672I5G
✅ ドロップイン✓ 在庫あり
$108 / 個
データシートを見る →10CX105YF672C8G
✅ ドロップイン📋 参考代替品（カタログ未掲載）
10CX105YF672I7G
✅ ドロップイン📋 参考代替品（カタログ未掲載）
10CX105YU484I5G
✅ ドロップイン✓ 在庫あり
$954.5455 / 個
データシートを見る →10CX105YF672E5G 最大定格＆電気的特性
| Family | Cyclone 10 GX |
| Logic Elements | 104000 |
| Number of Registers | 152000 |
| Total Block RAM | 7640 Kbit |
| Number of Block RAM Blocks | 382 |
| Number of Multipliers (18x19) | 250 |
| Number of PLLs/DLLs | 6 |
| User I/Os | 236 |
| Operating Supply Voltage (Core) | 0.9 V |
| Process Technology | 20 nm |
| Program Memory Type | SRAM |
| パッケージ | 672-BBGA, FCBGA |
| 実装タイプ | Surface Mount |
| Device Logic Units | 104000 |
| RoHS ステータス | Compliant (EU RoHS per Arrow listing) |
| HTS Code | 8542.31.00.60 |
10CX105YF672E5G 672-bbga, fcbga ピン配置ガイド
10CX105YF672E5G (672-bbga, fcbga パッケージ) のピン配置。 このデジタルICには、GPIO、通信インターフェース (UART、SPI、I2C)、および電源ピンが含まれています。代替ピン機能と設定オプションについては、メーカーのデータシートを参照してください。組み込みシステム設計とPCBレイアウトに不可欠です。
詳細なピン配置データはありません: 10CX105YF672E5G.
詳細は データシート をご参照ください。
主な用途
10CX105YF672E5G の用途: 6 件s: Industrial Machine Vision, Video Bridging and Protocol Conversion, Wireless Backhaul and Small Cell, Motor Control and Industrial Drive, IoT Edge Aggregation Gateway, Test and Measurement Instrumentation.
Industrial Machine Vision
The 10CX105YF672E5G fits machine vision pipelines because its 104K logic elements and 250 18x19 multipliers can process multi-megapixel sensor streams at line rate, while its 7,640 Kbit of embedded SRAM provides on-chip frame-line buffers without external DRAM thrash. With six PLLs/DLLs, designers can derive independent pixel clocks, exposure triggers, and encoder pulses from a single reference oscillator. Compared with general-purpose microcontrollers, the FPGA's parallel datapath sustains higher throughput at lower latency for Bayer-to-YUV conversion, lens correction, and thresholding in factory automation. The device's industrial-grade variants share the same silicon, allowing PCB reuse across temperature classes.
おすすめ
Video Bridging and Protocol Conversion
The 10CX105YF672E5G's mix of transceivers, LVDS-capable I/O, and 236 user pins suits HDMI-to-MIPI, SDI-to-displayport, or HDMI-to-LVDS bridging. With 382 block RAM blocks and 250 multipliers, designers can build scaling engines, color-space converters, and audio embedders in soft logic while keeping deterministic latency. The Cyclone 10 GX 20 nm process keeps dynamic power manageable even at 1080p60 video rates. Compared with ASSP bridge chips, the FPGA remains programmable for evolving pixel-clock and color-depth standards, extending product lifecycles.
おすすめ
Wireless Backhaul and Small Cell
With its on-chip transceivers and high DSP multiplier count, the 10CX105YF672E5G supports small-cell baseband, CPRI front-haul, and low-cost wireless backhaul modems. The 7,640 Kbit of embedded memory accommodates interleaver tables and short FEC blocks, while the 20 nm process keeps board power budgets compatible with PoE+ or solar-fed outdoor enclosures. Its hardened PCIe Gen2 hard IP lets designers pair it with an application processor over a low-pin-count interconnect, reducing PCB complexity. The 672-ball FCBGA also provides the signal-integrity headroom required for multi-gigabit serial links.
おすすめ
Motor Control and Industrial Drive
The 10CX105YF672E5G's six PLLs/DLLs, 236 user I/Os, and 250 DSP multipliers are well-matched to multi-axis field-oriented control (FOC), servo drives, and robotic arm controllers. Engineers can implement current-loop control under 4 usus per axis in soft logic while reserving multipliers for Park/Clarke transforms and space-vector PWM. The 7,640 Kbit of embedded SRAM fits encoder-capture histories and adaptive filter state. Compared with discrete MCU+DSP architectures, the FPGA delivers deterministic latency across all axes, eliminating timing jitter that causes torque ripple.
おすすめ
IoT Edge Aggregation Gateway
The 10CX105YF672E5G aggregates multiple industrial sensor buses (RS-485, CAN, SPI, I2C, Modbus) into a single Ethernet or cellular uplink. With 236 user I/Os, designers can connect 20+ bus transceivers directly to the FPGA, while 250 multipliers support on-chip AES, CRC, and TLS-acceleration primitives. The 7,640 Kbit embedded SRAM handles packet buffers and queue descriptors without external memory. Compared with microcontroller-only designs, the FPGA scales to dozens of concurrent bus masters and deterministic sampling, which is critical for time-sensitive industrial networks.
おすすめ
Test and Measurement Instrumentation
The 10CX105YF672E5G's combination of fast transceivers, plentiful multipliers, and 382 block RAM blocks makes it a strong fit for protocol-aware logic analyzers, pattern generators, and bit-error-rate testers. The 20 nm ALM architecture supports deep capture buffers and real-time triggering, while six PLLs/DLLs provide independent timing domains for receiver and transmitter. Compared with off-the-shelf instrumentation ASICs, the FPGA keeps the platform upgradeable as standards evolve, extending ROI over multi-year product lifecycles. Its 236 user I/Os also support high-channel-count parallel probe interfaces.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: 10CX105YF672E5G — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | 10CX105YF672I6G | 10CX105YF672E6G | 10CX105YF672I5G | 10CX105YF672C8G | 10CX105YF672I7G |
|---|---|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel | Intel | Intel |
| Package | 672-BBGA, FCBGA | 672-BBGA, FCBGA (same) | 672-BBGA, FCBGA (same) | 672-BBGA, FCBGA (same) | 672-BBGA, FCBGA (same) | 672-BBGA, FCBGA (same) |
| Logic Elements | 104000 | 104000 | 104000 | 104000 | 104000 | 104000 |
| Number of Registers | 152000 | 152000 | 152000 | 152000 | 152000 | 152000 |
| Embedded Memory (Kbit) | 7640 | 7640 | 7640 | 7640 | 7640 | 7640 |
| Number of Block RAM Blocks | 382 | 382 | 382 | 382 | 382 | 382 |
| Number of Multipliers (18x19) | 250 | 250 | 250 | 250 | 250 | 250 |
| Number of PLLs/DLLs | 6 | 6 | 6 | 6 | 6 | 6 |
| User I/Os | 236 | 236 | 236 | 236 | 236 | 236 |
| Core Voltage | 0.9 V | 0.9 V | 0.9 V | 0.9 V | 0.9 V | 0.9 V |
| Temperature Grade | Commercial (E5) | Industrial (I6) | Commercial (E6) | Industrial (I5) | Commercial (C8) | Industrial (I7) |
| Process Technology | 20 nm | 20 nm | 20 nm | 20 nm | 20 nm | 20 nm |
主な差別化要因
- Highest commercial-temperature speed grade 5 variant of the 104K-LE Cyclone 10 GX in F672 package （vs 10CX105YF672E6G)
- Industrial-grade pin-compatible drop-in upgrade available for harsh environments （vs 10CX105YF672I6G)
- Large embedded SRAM capacity for on-chip frame buffering （vs 10CX085YF672E5G)
設計ノート
Plan power sequencing carefully for the 10CX105YF672E5G: the 0.9 V core must ramp before the 1.8 V/2.5 V/3.3 V I/O banks to prevent I/O pin back-powering through the ESD diodes. Use a dedicated power-supply sequencer such as the Intel EN63A0CA or a discrete RC/MOSFET ramp circuit; do not rely on diode-ORed rails. Transceiver analog supplies (1.0 V VCCT, 1.2 V VCCR) require separate low-noise LDOs and star-ground routing. Bulk decoupling per Intel's PDN design guidelines is essential for multi-gigabit serial-link jitter performance.
Estimated: at full utilization the 10CX105YF672E5G can dissipate 4-6 W depending on toggle rate and clock tree usage. With a theta_JA of roughly 12-15 C/W for the 672-ball FCBGA (per typical Cyclone 10 GX thermal models), junction temperature can rise 50-90 C above ambient at full load. Mount a 4-layer PCB with continuous ground pour under the package and consider a small heat spreader or thermal interface material for enclosed industrial enclosures. Verify with the Cyclone 10 GX thermal model AN-797 available on Intel's FPGA design resource center.
Use a 12-layer (or minimum 8-layer) stack-up for the 672-ball FCBGA to keep microstrip-impedance-controlled traces for transceivers (100 ohm differential) and DDR3 memory interfaces (50 ohm single-ended). Route all high-speed serial links on the top or just below-top layer over a continuous reference plane, with no signal splits. BGA break-out should use the dog-bone or via-in-pad pattern recommended in the Intel Cyclone 10 GX pin connection guidelines; via-in-pad is preferred for dense transceivers and DDR3.
For multi-gigabit transceivers, follow Intel's IBIS-AMI models and use 3D electromagnetic field-solver simulation for vias and connector transitions. Pre-emphasis and equalization settings must be tuned per channel; default Quartus Prime settings are conservative. For DDR3 interfaces, enforce matched-length trace routing within +/-25 mil and use fly-by topology with proper termination VTT at the end of the fly-by. Do not route high-speed signals across plane splits.
Common pitfalls when designing with the 10CX105YF672E5G include: (1) sharing configuration JTAG pins as GPIO without re-considering the configuration scheme, (2) using the wrong MSEL pin pull-up/pull-down values for the desired configuration mode (AS, PS, JTAG), (3) ignoring the device's required POR (power-on-reset) timing before releasing nCONFIG, and (4) assuming the Cyclone 10 GX silicon matches Cyclone V silicon in soft IP - many soft IP cores must be re-built in Quartus Prime. Always start with an Intel reference design as a base and validate power sequencing before bringing up transceivers.
コンプライアンス情報
EU RoHS compliant per Arrow Electronics product listing. AEC-Q100 not applicable - this is an FPGA, not an automotive-grade IC; AEC-Q100 qualification would require the -Q suffix automotive variant. Halogen-free status not explicitly listed in verified data - refer to Intel material declaration for confirmation.