10CX105YF672I5G - Cyclone 10 GX FPGA, 104K LE, F672 | Intel
MPN: 10CX105YF672I5G ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $158.06 | $158.06 |
| 10 | $145.5 | $1,455.00 |
| 100 | $132 | $13,200.00 |
| 500 | $119.5 | $59,750.00 |
| 1,000 | $108 | $108,000.00 |
Drop-in alternatives for 10CX105YF672I5G — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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10CX105YF672I6G
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View Datasheet →10CX105YF672E5G
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View Datasheet →10CX105YF672E6G
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View Datasheet →10CX085YF672I5G
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View Datasheet →10CX105YF672I5G Maximum Ratings & Electrical Characteristics
| Family | Cyclone 10 GX |
| Logic Elements (LE) | 104,000 |
| Embedded Memory (bits) | 8,641,536 |
| Adaptive Logic Modules (ALM) | 39,240 (estimated from 104K LE) |
| 18x19 Multipliers | 156 |
| Maximum User I/O | 236 |
| Transceivers | Up to 12 (PCIe Gen2 capable) |
| Maximum Transceiver Data Rate | 12.5 Gbps |
| Hard PCI Express Blocks | 1 (Gen2 x1/x2/x4) |
| Hard Memory Controllers | DDR3, DDR4, LPDDR3 |
| Process Technology | 20 nm |
| Package | 672-ball FCBGA (F672) |
| Package Pitch | 1.0 mm |
| Operating Temperature | -40C to +100C (Industrial) |
| Mounting Type | Surface Mount (BGA) |
| MSL Level | 3 |
| RoHS Status | Compliant |
| Supply Voltage (Core) | 0.9 V (typical) |
| Supply Voltage (I/O) | 1.2 V to 3.0 V (multi-voltage I/O) |
10CX105YF672I5G 1.0 mm Pin Configuration Guide
Complete pinout information for 10CX105YF672I5G (1.0 mm package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for 10CX105YF672I5G.
Refer to the datasheet for full pin configuration.
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
10CX105YF672I5G is suitable for 7 applications: Industrial Machine Vision Systems, Wireless Backhaul Equipment, Broadcast Video Interfaces (12G-SDI/HDMI 2.0), PCIe Acceleration Cards, Factory Automation and Motor Control, Medical Imaging Equipment, IoT Edge Gateways.
Industrial Machine Vision Systems
The 10CX105YF672I5G is well suited for industrial machine vision systems requiring real-time image processing at multiple Gigapixel/second throughput. Its 104,000 logic elements and 156 18x19 multipliers provide ample capacity for Sobel, Laplacian, and convolutional preprocessing pipelines operating on 4K sensor streams. The integrated 12.5 Gbps transceivers handle CoaXPress-12 (CXP-12) and 10 GigE Vision interfaces without consuming soft logic. Compared with smaller Cyclone 10 GX parts (10CX085, 10CX055), the 10CX105 supports higher sensor resolutions and multi-camera aggregation. Typical designs place DDR4 memory on the hard memory controller for frame buffering, and use PCIe Gen2 x4 for host communication in industrial PCs.
Recommended
Wireless Backhaul Equipment
The 10CX105YF672I5G enables low-cost wireless backhaul designs with its 12 integrated transceivers supporting CPRI (Common Public Radio Interface) rates up to option 7 (9.83 Gbps). With 104K logic elements, designers can implement baseband processing, fronthaul CPRI encapsulation, and synchronous Ethernet clock recovery on a single chip. The hard PCIe Gen2 block connects to baseband SoCs for distributed unit (DU) architectures. Compared with implementing CPRI in soft logic on smaller FPGAs, the 10CX105's hardened transceiver PCS reduces latency by 30-50% and saves 20K+ logic elements. Industrial temperature grade (-40C to +100C) supports outdoor tower-mounted deployments.
Recommended
Broadcast Video Interfaces (12G-SDI/HDMI 2.0)
The 10CX105YF672I5G integrates up to 12 transceivers capable of 12 Gbps data rates, making it ideal for broadcast video interfaces including 12G-SDI, HDMI 2.0, and DisplayPort 1.4. With 104K logic elements, designers can implement video format conversion, color space conversion, HDR processing, and audio embedding on a single device. The hardened transceiver PCS eliminates soft logic serializer/deserializer (SERDES) overhead, achieving sub-100 ns latency required for live broadcast production. Compared with implementing SERDES in soft logic on Cyclone V FPGAs, the Cyclone 10 GX achieves 4x higher data rates with half the power per gigabit.
Recommended
PCIe Acceleration Cards
The 10CX105YF672I5G is designed into PCIe Gen2 x4 endpoint acceleration cards for industrial PCs and edge servers. Its hard PCIe Gen2 IP block (x1/x2/x4 lane support) eliminates the soft PCIe IP core typically consuming 15-25K logic elements, freeing those resources for custom acceleration logic. With 104K logic elements, designers can implement custom DSP pipelines, machine learning inference accelerators, or FPGA-managed NVMe controllers. Industrial temperature grade enables operation in non-data-center environments. Compared with PCIe soft IP on smaller Cyclone 10 GX parts, the hard IP reduces latency and saves approximately 20K logic elements for application logic.
Recommended
Factory Automation and Motor Control
The 10CX105YF672I5G supports multi-axis factory automation and motor control designs requiring high-precision PWM generation, encoder interfaces (EnDat 2.2, BiSS, Tamagawa), and industrial Ethernet protocols (EtherCAT, PROFINET, EtherNet/IP). With 104K logic elements, designers can implement control loops for 4-8 axes on a single device. Industrial temperature grade (-40C to +100C) and IEC 61508 SIL-2 capable development flow make it suitable for safety-related automation. Compared with discrete MCU + ASIC architectures, the FPGA-based approach reduces PCB area by 50-70% and enables field upgrades for protocol updates.
Recommended
Medical Imaging Equipment
The 10CX105YF672I5G is used in medical imaging modalities including ultrasound beamforming, endoscopy, and point-of-care imaging where low power and high DSP throughput are critical. Its 156 18x19 multipliers enable efficient digital beamforming, FIR filtering, and image enhancement pipelines at sub-50W power consumption. The 12 transceivers handle high-speed ADC JESD204B links at 6-8 Gbps per lane for direct sampling ADCs. Compared with ASIC implementations, the FPGA approach accelerates time-to-market and supports field upgrades for new imaging modes. Medical applications should verify compliance with IEC 60601-1 and FDA quality system regulations.
Recommended
IoT Edge Gateways
The 10CX105YF672I5G enables IoT edge gateways with hardware-accelerated protocol translation between industrial fieldbus (Modbus, CAN, RS-485) and cloud connectivity (MQTT over Ethernet). With 104K logic elements, designers can implement secure boot, TLS 1.3 acceleration, and local data preprocessing before cloud upload. Industrial temperature grade and low power (approximately 5-8W typical) make it suitable for DIN-rail mounted industrial gateways. Compared with high-end processors, the FPGA-based approach reduces latency for time-sensitive control loops and provides deterministic response under network congestion.
Recommended
Recommended Products Summary
Engineering reference data for 10CX105YF672I5G — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | 10CX105YF672I6G | 10CX105YF672E5G | 10CX105YF672E6G | 10CX085YF672I5G | 10CX085YF672I6G |
|---|---|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel | Intel | Intel |
| Package | 672-ball FCBGA (F672) | 672-ball FCBGA (F672) | 672-ball FCBGA (F672) | 672-ball FCBGA (F672) | 672-ball FCBGA (F672) | 672-ball FCBGA (F672) |
| Logic Elements | 104,000 | 104,000 | 104,000 | 104,000 | 85,000 (-18%) | 85,000 (-18%) |
| Embedded Memory (bits) | 8,641,536 | 8,641,536 | 8,641,536 | 8,641,536 | [DATA_NEEDED: 85K LE memory] | [DATA_NEEDED: 85K LE memory] |
| Speed Grade | I5 (mid) | I6 (fast) | E5 (extended temp, mid speed) | E6 (extended temp, fast) | I5 (mid) | I6 (fast) |
| Temperature Grade | Industrial (-40C to +100C) | Industrial | Extended (0C to +85C) | Extended (0C to +85C) | Industrial | Industrial |
| Maximum Transceivers | 12 | 12 | 12 | 12 | [DATA_NEEDED: 85K LE transceivers] | [DATA_NEEDED: 85K LE transceivers] |
| Maximum I/O Pins | 236 | 236 | 236 | 236 | [DATA_NEEDED: 85K LE I/O] | [DATA_NEEDED: 85K LE I/O] |
Key Differentiators
- Largest Cyclone 10 GX member with maximum 104K logic elements (vs 10CX085YF672I5G)
- Industrial temperature grade for harsh environments (vs 10CX105YF672E5G)
- Mid-speed I5 grade balances performance and cost (vs 10CX105YF672I6G)
Design Notes
The 10CX105YF672I5G dissipates approximately 5-15W typical in industrial applications with full transceiver and DSP utilization. With a theta_JB of approximately 0.5 C/W and theta_JA of 12-15 C/W on a JEDEC JESD51-7 8-layer PCB, the junction-to-ambient thermal resistance requires thermal vias under the BGA center thermal pad, connected to internal ground planes and a bottom-side copper spreader. For continuous transceiver use at 10+ Gbps, design with theta_JA of 8-10 C/W using a 1 oz copper inner plane array and 0.5 oz bottom-side spreader. Forced-air cooling (1 m/s minimum) is recommended for applications with sustained 95%+ transceiver utilization.
Transceiver reference clock jitter directly impacts high-speed serial link performance. For 10.3125 Gbps data rates, use a sub-500 fs RMS jitter clock source such as the SiTime SiT9501 or Skyworks SKY73759. PCB-controlled impedance requires 85 ohm differential routing for transceiver channels and 100 ohm differential for PCIe - use a 4-layer PCB minimum with stripline routing between ground planes for best results. Per Intel Cyclone 10 GX guidelines, maximum transceiver trace mismatch is 5 mils (0.127 mm) for differential pairs, with via stub length under 12 mils.
The F672 package uses a 1.0 mm ball pitch FCBGA - PCB design requires 0.4 mm via-in-pad microvias for breakout, 0.5/0.2 mm trace/space design rules, and a minimum 6-layer stackup with two dedicated ground planes. Mount the part on top of the PCB with the thermal pad exposed (no solder mask over thermal balls) for best heat dissipation. Decoupling requires 100 nF X7R ceramic capacitors per power pin (8-12 total), with 10 uF bulk capacitors placed within 1 cm of the device. Use Intel's Cyclone 10 GX symbol library in Altium Designer or Cadence Allegro to ensure pinout accuracy.
Do not use the 10CX105YF672I5G in 3.3V-only I/O designs if any GPIO must support 1.2V or 1.5V standards - the I/O banks support 1.2V to 3.0V multi-voltage operation. Configuration requires an external flash (EPCQ256 or compatible QSPI) for production - the FPGA does not retain configuration on power cycle. For JTAG programming, leave TCK, TDI, TDO, TMS, and CONFIG_DONE accessible for factory programming. Always include a 100 ms power-on reset circuit on nCONFIG to ensure clean configuration startup.
Estimated: power-supply design for the 10CX105YF672I5G requires 0.9V core (up to 10A transient), 1.8V transceiver PLL analog (low-noise LDO required, LTM4622 or similar), 1.8V/2.5V/3.0V I/O banks, and 1.2V auxiliary. Total system power is approximately 8-12W typical and 18W peak during full transceiver and DSP utilization. Use a 4-phase buck regulator for the core supply and isolated POL converters for transceiver PLL. Power supply rejection requirement is 60 dB at 1 MHz for the analog supply - use an LTM4628 or TPS74401 with additional LC filtering.
Compliance Information
RoHS compliant per Intel product page. Industrial temperature grade (-40C to +100C) but not AEC-Q100 qualified for automotive safety applications. Halogen-free status unknown from public datasheet - contact Intel for confirmation.
