10CX105YF672E6G - Cyclone 10 GX FPGA, 105K LE, 672-FBGA | Intel / Altera
MPN: 10CX105YF672E6G ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $113.071 | $113.07 |
| 10 | $107.686 | $1,076.86 |
| 100 | $102.558 | $10,255.80 |
| 500 | $100.547 | $50,273.50 |
| 1,000 | $100.547 | $100,547.00 |
Drop-in alternatives for 10CX105YF672E6G — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
10CX150YF672E6G
✅ Drop-In✓ In Stock
$124.9 / Unit
View Datasheet →10CX105YF672E5G
✅ Drop-In✓ In Stock
$310 / Unit
View Datasheet →10CX085YF672E6G
✅ Drop-In✓ In Stock
$280.5 / Unit
View Datasheet →10CX105YF672I6G
✅ Drop-In✓ In Stock
$338 / Unit
View Datasheet →10CX105YF672E7G
✅ Drop-In ⚠️ 参数待验证📋 Reference alternative (not in catalog)
10CX105YU484E6G
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$65.8 / Unit
View Datasheet →10CX105YF672E6G Maximum Ratings & Electrical Characteristics
| Series | Cyclone® 10 GX |
| Device Family | Cyclone 10 GX |
| Logic Elements (LE) | 105,000 |
| Logic Cells | 104,000 |
| Adaptive Logic Modules (ALM) | 38,000 |
| Embedded Memory | 8.439 Mbit (8,641,536 bits) |
| User I/Os | 236 |
| Core Operating Voltage | 0.9 V |
| Speed Grade | -6 (commercial) |
| Operating Temperature | 0 °C to +100 °C |
| Package | 672-BBGA, FCBGA (F672) |
| Mounting Type | Surface Mount (SMD/SMT) |
| Packaging | Tray |
| Process Node | 20 nm (TSMC) |
| RoHS Status | Compliant |
| Design Software | Quartus Prime Standard |
10CX105YF672E6G 672-bbga, fcbga (f672) Pin Configuration Guide
Complete pinout information for 10CX105YF672E6G (672-bbga, fcbga (f672) package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for 10CX105YF672E6G.
Refer to the datasheet for full pin configuration.
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
10CX105YF672E6G is suitable for 7 applications: Industrial Video Bridging and Machine Vision, Low-Cost PCIe Gen2 Endpoint Cards, IoT Edge Acceleration Gateways, Factory Automation and Motion Control, Broadcast and Pro-AV Signal Processing, Software-Defined Radio and Wireless Baseband, Medical Imaging and Diagnostic Equipment.
Industrial Video Bridging and Machine Vision
The 10CX105YF672E6G fits industrial video bridging and machine-vision pipelines because it combines 105K logic elements with hardened PCI Express Gen2 and up to 12.5 Gbps transceivers in a 672-ball FCBGA. At typical machine-vision loads (one MIPI/CSI-2 bridge to GigE Vision, 1080p at 60 fps), the device uses roughly 60-70% of its ALMs and ~5 Mbit of block RAM, leaving headroom for image-processing kernels and a soft RISC-V or Nios II processor. Its 236 user I/Os accommodate parallel camera interfaces, GPIO, and DDR3 external memory controller logic. Compared with a Cyclone V equivalent, the Cyclone 10 GX reduces static power by roughly 30-40% on the same node generation, enabling fanless vision-controller designs in 24V industrial backplanes.
Recommended
Low-Cost PCIe Gen2 Endpoint Cards
The 10CX105YF672E6G is well suited to low-cost PCIe Gen2 endpoint cards because it integrates a hardened PCI Express Gen2 controller (x1/x4) plus 12.5 Gbps transceivers in the same silicon. At PCIe Gen2 x4, the device achieves line rate without burning soft IP, freeing 40-60K logic elements for application logic. The 672-ball FCBGA footprint supports standard add-in-card layouts (half-height, half-length) and the 0.9 V core rail simplifies LDO selection on the host board. Designers building data-acquisition or software-defined-radio endpoints commonly select this density for its balance of cost and feature integration.
Recommended
IoT Edge Acceleration Gateways
The 10CX105YF672E6G fits IoT edge acceleration gateways because the Cyclone 10 GX family targets low static power and integrates hardened PCIe Gen2 with high-speed transceivers in the same die. Typical edge-gateway designs offload pre-processing (encryption, protocol translation, simple ML inference) into FPGA fabric and consume roughly 30-50% of the 105K LE. The 0.9 V core rail and -6 speed grade balance thermal performance with fanless industrial enclosure requirements. Compared with a Cyclone V 5CEFA9 equivalent, the 10CX105 delivers roughly 1.5x logic per watt on the same 0.9 V rail, which is critical for sealed IP65 edge nodes.
Recommended
Factory Automation and Motion Control
The 10CX105YF672E6G is well matched to factory automation and motion-control applications where deterministic latency, multi-axis PWM, and protocol bridging (EtherCAT, PROFINET, EtherNet/IP) are required. At typical loads (one EtherCAT master + 8-axis PWM + safe-torque-off logic), the device uses roughly 50-65K LE and the -6 speed grade supports 100 MHz EtherCAT with margin. The 236 user I/Os are sufficient for multi-encoder inputs and parallel digital I/O, while the 0.9 V core and -E6 commercial temperature (0-100 °C) suit sealed control-cabinet designs. Designers migrating from Cyclone IV/V often choose Cyclone 10 GX for the lower static power and hardened PCIe for host connectivity.
Recommended
Broadcast and Pro-AV Signal Processing
The 10CX105YF672E6G is a natural fit for broadcast and pro-AV signal-processing applications because it integrates 12.5 Gbps transceivers for SDI (3G/6G/12G-SDI), HDMI 2.0 bridging, and 4K video pipelines in a single 672-ball FCBGA. At a 4K60 4:2:2 pipeline with light color-space conversion and audio embedding, the device typically consumes 40-60% of its 105K LE and a few Mbit of block RAM. The -6 speed grade supports the Fmax required for 12G-SDI serialization and parallel-pixel processing, while 236 user I/Os handle auxiliary GPIO, I2C, and SPI control. Compared with prior-generation Cyclone V designs, the Cyclone 10 GX adds hardened PCIe for capture-card host interface without burning soft IP.
Recommended
Software-Defined Radio and Wireless Baseband
The 10CX105YF672E6G supports software-defined radio and wireless-baseband applications because the Cyclone 10 GX integrates up to 12.5 Gbps transceivers with hardened PCI Express Gen2 for host transport, plus DSP blocks for FFT and channelization. At a 4x4 MIMO LTE small-cell baseband or a 5G sub-6 small-cell fronthaul, the device uses roughly 70-85K LE and 5-7 Mbit of block RAM, leaving margin for soft IP and a Nios II control plane. The 236 user I/Os accommodate parallel data converters (JESD204B), GPIO, and external memory interfaces. Designers targeting smaller SISO radio designs often step down to the 10CX085YF672E6G, while larger 8x8 or carrier-aggregation systems move up to the 10CX150YF672E6G, all on the same F672 footprint.
Recommended
Medical Imaging and Diagnostic Equipment
The 10CX105YF672E6G is appropriate for medical-imaging and diagnostic equipment such as portable ultrasound and endoscopy processors because the Cyclone 10 GX combines high logic density, hardened PCIe, and low static power at 0.9 V in a 672-ball FCBGA. At typical portable-ultrasound channel-processing loads (32-channel beamformer with CW Doppler), the device consumes roughly 50-65K LE and several Mbit of block RAM. The -E6 commercial temperature grade (0-100 °C) suits cart-based ultrasound, while the -I6 industrial variant supports refrigerated lab instrumentation. The integrated 12.5 Gbps transceivers enable direct MIPI CSI-2 / SLVS-EC sensor bridges and high-resolution displays without external SerDes chips.
Recommended
Recommended Products Summary
Engineering reference data for 10CX105YF672E6G — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | 10CX150YF672E6G | 10CX105YF672E5G | 10CX085YF672E6G | 10CX105YF672I6G | 10CX105YF672E7G | 10CX105YU484E6G |
|---|---|---|---|---|---|---|---|
| Brand | Intel / Altera | Intel / Altera | Intel / Altera | Intel / Altera | Intel / Altera | Intel / Altera | Intel / Altera |
| Package | 672-BBGA, FCBGA (F672) | 672-BBGA, FCBGA (F672) — same | 672-BBGA, FCBGA (F672) — same | 672-BBGA, FCBGA (F672) — same | 672-BBGA, FCBGA (F672) — same | 672-BBGA, FCBGA (F672) — same | 672-BBGA, FCBGA (F672) — same |
| Logic Elements (LE) | 105,000 | 150,000 | 105,000 | 85,000 | 105,000 | 105,000 | 105,000 |
| Adaptive Logic Modules (ALM) | 38,000 | ≈54,000 | 38,000 | ≈31,000 | 38,000 | 38,000 | 38,000 |
| Embedded Memory | 8.439 Mbit | ≈12.2 Mbit | 8.439 Mbit | ≈6.8 Mbit | 8.439 Mbit | 8.439 Mbit | 8.439 Mbit |
| User I/Os | 236 | 236 | 236 | 236 | 236 | 236 | 236 |
| Speed Grade | -6 (commercial) | -6 | -5 (faster Fmax) | -6 | -6 | -7 (slower Fmax) | -6 |
| Operating Temperature | 0 °C to +100 °C (commercial) | 0 °C to +100 °C | 0 °C to +100 °C | 0 °C to +100 °C | -40 °C to +100 °C (industrial) | 0 °C to +100 °C | 0 °C to +100 °C |
| Core Voltage | 0.9 V | 0.9 V | 0.9 V | 0.9 V | 0.9 V | 0.9 V | 0.9 V |
Key Differentiators
- Pin-compatible higher-density option in the same F672 package (vs 10CX150YF672E6G)
- Pin-compatible lower-density option for cost reduction (vs 10CX085YF672E6G)
- Industrial-temperature pin-compatible variant (vs 10CX105YF672I6G)
Design Notes
The 10CX105YF672E6G requires a 0.9 V core supply plus separate auxiliary and transceiver PLLs/rails. Use a minimum 4-layer PCB with dedicated power planes; route the 0.9 V core plane directly under the package thermal ball array. Decouple with 0402/0201 ceramics placed within the manufacturer's via-in-pad pattern — typically 22 µF bulk + 100 nF + 10 nF per supply pin group as recommended in the Cyclone 10 GX family datasheet. Estimate: at 100 % toggle rate and full transceiver utilization, total power dissipation typically lands in the 6-10 W range, so use a thermally bonded FCBGA with at least 4 thermal vias per ball pattern.
The 672-ball FCBGA uses a 1.0 mm ball pitch with full-array thermal balls under the die. PCB fabrication requires laser-drilled microvias (0.1 mm/4 mil) or stacked-via construction per the Cyclone 10 GX package file. Estimated: 6-8 PCB layers are typical for a clean reference design with transceiver routes; fewer layers risk excessive crosstalk on the 12.5 Gbps transceiver channels. Match trace lengths to within the limits specified in the device handbook (typically within 150 mil for 6 Gbps and tighter for 12.5 Gbps channels).
Do not confuse the F672 package with the U484 or F484 packages — they are different footprints and not pin-compatible. Cyclone 10 GX speed grades -5/-6/-7 trade off Fmax vs power; the -5 grade is recommended for tightest timing margin, the -7 grade for power-constrained designs that do not need maximum Fmax. Configuration: use JTAG (USB-Blaster) for development and an EPCQ-L or QSPI flash for production. Without proper configuration mode setup in Quartus Prime, the device will fail to initialize — verify MSEL pins match the desired configuration mode before power-up.
Estimated junction-to-ambient thermal resistance for the 672-ball FCBGA on a standard 8-layer PCB with adequate thermal vias is roughly 12-18 °C/W depending on airflow. At a 8 W typical design, junction temperature rises 100-140 °C above ambient — adequate for the 0-100 °C commercial range but with limited margin. For sealed enclosures with no airflow, derate to 6-7 W or move to the lower-density 10CX085YF672E6G. Always validate thermal performance with the Cyclone 10 GX PowerPlay early-power-estimator spreadsheet before committing to layout.
Transceiver channels up to 12.5 Gbps require controlled-impedance routing (typically 85 Ω differential) with no more than two connector breaks per channel; AC-coupling capacitors (typically 100 nF) must be placed close to the receiver side. Reference clocks to the transceivers should be sourced from a low-jitter oscillator (< 100 fs RMS for 10 Gbps links). For external memory interfaces (DDR3/DDR4), follow the Cyclone 10 GX External Memory Interface (EMIF) handbook — improper termination or fly-by routing is the most common cause of memory-interface bit-error-rate failures.
Compliance Information
RoHS compliance confirmed via DigiKey product listing. REACH, halogen-free, and conflict-minerals statements not directly published on the reviewed distributor pages — treat as unknown unless confirmed by an Intel product-compliance letter.
