ADC101S101CISDX - 10-Bit 1MSPS SAR ADC, 6-WSON | Texas Instruments
部品番号: ADC101S101CISDX ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $1.78 | $1.78 |
| 10 | $1.55 | $15.50 |
| 100 | $1.28 | $128.00 |
| 500 | $1.05 | $525.00 |
| 1,000 | $0.89 | $890.00 |
| 3,000 | $0.72 | $2,160.00 |
ADC101S101CISDX 概要
A SAR ADC (Successive-Approximation Register Analog-to-Digital Converter) is a type of ADC that uses a binary-search algorithm through an internal DAC and comparator to digitize an analog input one bit at a time per clock cycle. SAR ADCs are prized for low latency, deterministic conversion time, and excellent DC accuracy without the pipeline delay or switching-noise artifacts of higher-speed pipeline or delta-sigma architectures. Within the data-converter hierarchy, the ADC101S101 sits between general-purpose 8/10-bit SARs and higher-resolution 12/14-bit precision SARs.
Key features of the ADC101S101 include a single-ended analog input range of 0 V to VDD, straight-binary serial output, an external serial clock up to 20 MHz, and an industrial-grade operating range of -40 °C to +85 °C. The CISDX suffix denotes the 6-WSON (also called LLP-6 / HVSON-6) tape-and-reel packaging variant, which offers an extremely small 2.2 x 2.5 mm footprint ideal for space-constrained PCB designs.
The architecture is based on a charge-redistribution SAR core with an internal track-and-hold, sample-and-hold capacitor, and a synchronous serial output stage. Because the part performs a full conversion in 16 clock cycles, total conversion latency at 1 MSPS is only 16 clocks, and the part supports burst-mode sampling for sequential conversions.
Typical applications include portable instrumentation, sensor-signal digitization, process control, and consumer audio front ends where 10-bit resolution at 1 MSPS is sufficient. The wide supply range also suits industrial 5 V and 3.3 V mixed-rail designs, and the small footprint makes it popular in dense data-acquisition PCBs.
When designing with this ADC, ensure that the analog input source has low output impedance and that the reference decoupling capacitor is placed within 5 mm of the VDD pin. The SCLK input is tolerant of 5 V signals even when VDD is 3.3 V, simplifying level translation.
This page synthesizes distributor pricing, pin-compatible drop-in alternatives, and practical design notes not found in the manufacturer datasheet, helping engineers select the right part and avoid common pitfalls.
ドロップイン代替品: ADC101S101CISDX — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: ADC101S101CISDX （同一形状・フットプリント） — 相違点: Resolution, Package, RoHS Status, Sample Rate Range, Operating Temperature.
クイック比較ツール — 並列比較する代替部品を選択:
ADC101S101CISDX/NOPB
✅ ドロップイン✓ 在庫あり
$1.32 / 個
データシートを見る →ADC101S021CISDX
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$1.32 / 個
データシートを見る →ADC121S101CISDX
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
ADC121S021CISDX
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$1.85 / 個
データシートを見る →ADC121S051CISDX
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$1.55 / 個
データシートを見る →ADC101S101CISDX 最大定格＆電気的特性
| 分解能 | 10 bits |
| Number of Channels | 1 |
| Sample Rate Range | 500 kSPS to 1 MSPS |
| Architecture | Successive-Approximation Register (SAR) |
| 電源電圧 | 2.7 V to 5.25 V |
| Power Consumption (3 V supply) | 2.0 mW (typical) |
| Power Consumption (5 V supply) | 10 mW (typical) |
| Analog Input Range | 0 V to VDD (single-ended) |
| Serial Interface | SPI, QSPI, MICROWIRE compatible |
| Maximum Serial Clock | 20 MHz |
| 動作温度範囲 | -40 °C to +85 °C |
| パッケージ | 6-WSON (2.2 x 2.5 mm), also called LLP-6 / HVSON-6 |
| 実装タイプ | Surface Mount |
| RoHS ステータス | Compliant |
| Lead-Free | Yes |
ADC101S101CISDX ピン構成
| ピン 1 | CH0 — Analog input channel 0 (single-ended, 0 V to VDD) |
| ピン 2 | GND — Ground (0 V reference for analog and digital) |
| ピン 3 | VDD — Power supply input, 2.7 V to 5.25 V |
| ピン 4 | DOUT — Serial data output (SPI/QSPI/MICROWIRE, straight binary) |
| ピン 5 | SCLK — Serial clock input (up to 20 MHz) |
| ピン 6 | CS — Chip select, active low (also used to power-down the part) |
主な用途
ADC101S101CISDX の用途: 7 件s: Portable Battery-Powered Sensor Digitization, Industrial Process Control Analog Input Modules, Consumer Audio Front-End Digitization, Data Acquisition Peripherals for FPGAs, Motor Control Feedback (Speed/Torque Sense), Medical Patient Monitoring Sensor Interface, IoT Sensor Nodes and Smart-Home Hubs.
Portable Battery-Powered Sensor Digitization
The ADC101S101CISDX is an excellent fit for battery-powered sensor readout modules where 10-bit resolution at up to 1 MSPS is sufficient. Its 2.0 mW typical power consumption at 3 V supply and sub-1 µA power-down current (CS held high) allow aggressive duty-cycling that extends coin-cell or Li-ion battery life substantially. The 6-WSON 2.2 x 2.5 mm package is small enough to place near the sensor, keeping analog traces short to minimize noise pickup. The 2.7 V-5.25 V supply flexibility lets the same ADC digitize signals from a 3.3 V MCU rail or a 5 V industrial sensor rail without level shifters.
おすすめ
Industrial Process Control Analog Input Modules
In 4-20 mA loop or 0-10 V industrial analog-input modules the ADC101S101CISDX provides a compact, low-cost means of digitizing one analog signal per chip. The wide 2.7 V-5.25 V supply lets it run directly from a 24 V-to-5 V derived rail, while the SAR architecture has no pipeline delay so a microcontroller can read the conversion the same cycle it is initiated. The -40 °C to +85 °C industrial operating range matches common factory-automation environments. Designers often place multiple ADC101S101CISDX parts in parallel (one per channel) when the system requires simultaneous-sampling-free, low-latency sequential reads.
おすすめ
Consumer Audio Front-End Digitization
Although the ADC101S101CISDX is a 10-bit SAR part, many consumer-audio front ends (toys, intercoms, low-cost Bluetooth speakers) require only telephony-bandwidth sampling at 8 kSPS to 44.1 kSPS, where 10-bit resolution is more than adequate. The part's straight-binary serial output streams naturally into I2S-like DSP ports or general-purpose SPI peripherals, and the small 6-WSON footprint keeps the BOM area minimal. Power consumption is low enough that the ADC can stay enabled throughout audio playback without noticeably impacting battery life in a portable speaker.
おすすめ
Data Acquisition Peripherals for FPGAs
The ADC101S101CISDX is widely used as a compact ADC for FPGA-based data-acquisition cards and logic-analyzer front-end digitizers. The 20 MHz SCLK capability allows 1 MSPS conversion rates when paired with FPGA generic I/O running at 50 MHz or faster. The straight-binary serial output is trivial to deserialize in Verilog/VHDL via a small FSM, and the deterministic 16-clock SAR latency simplifies timing closure. Designers appreciate the small 6-WSON footprint when dozens of analog channels must fit on a single PCB mezzanine card.
おすすめ
Motor Control Feedback (Speed/Torque Sense)
In BLDC or stepper-motor control loops the ADC101S101CISDX is often used to digitize current-sense amplifier outputs at sample rates above the PWM frequency (typically 20-50 kSPS is sufficient). The 500 kSPS-1 MSPS ceiling gives plenty of oversampling headroom to apply moving-average filtering, improving effective resolution to ~12 bits. The SAR architecture's deterministic single-cycle latency means the control loop sees a fresh sample each PWM period without pipeline-induced phase shift, simplifying loop compensation.
おすすめ
Medical Patient Monitoring Sensor Interface
Although non-isolated and 10-bit, the ADC101S101CISDX is sometimes used in low-cost patient-monitoring peripherals (pulse oximetry front-ends, body-temperature probes) where 10-bit resolution at 100-500 Hz sample rates suffices. Designers combine the part with an instrumentation amplifier and a digital isolator to keep the patient-side front end safe. The low 2 mW power dissipation keeps thermal rise inside the patient-contact housing minimal - important for skin-contact wearables. Note: this is for the analog-front-end signal-conditioning stage; do NOT use non-isolated ADCs directly across patient isolation barriers.
おすすめ
IoT Sensor Nodes and Smart-Home Hubs
The ADC101S101CISDX slots neatly into Wi-Fi or Bluetooth Low Energy IoT sensor nodes that need to digitize one or two analog sensor outputs (light, gas, soil moisture) for forwarding to a cloud backend. The 2.0 mW active power and sub-1 µA standby current suit battery-powered nodes that wake, sample, transmit, and sleep. The 2.7 V-5.25 V supply range lets it coexist with both 3.3 V MCUs and 5 V analog sensor rails without additional regulation. The 6-WSON footprint is small enough to fit on a coin-cell-powered wearable PCB.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: ADC101S101CISDX — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | ADC101S101CISDX/NOPB | ADC101S021CISDX | ADC121S101CISDX | ADC121S021CISDX | ADC121S051CISDX |
|---|---|---|---|---|---|---|
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Package | 6-WSON (2.2x2.5) | 6-WSON (2.2x2.5) - same | 6-WSON (2.2x2.5) - same | 6-WSON (2.2x2.5) - same | 6-WSON (2.2x2.5) - same | 6-WSON (2.2x2.5) - same |
| Resolution | 10 bits | 10 bits | 10 bits | 12 bits | 12 bits | 12 bits |
| Sample Rate Range | 500 kSPS to 1 MSPS | 500 kSPS to 1 MSPS | 200 kSPS to 500 kSPS | 500 kSPS to 1 MSPS | 200 kSPS to 500 kSPS | 200 kSPS to 500 kSPS |
| Architecture | SAR | SAR | SAR | SAR | SAR | SAR |
| Supply Voltage | 2.7 V to 5.25 V | 2.7 V to 5.25 V | 2.7 V to 5.25 V | 2.7 V to 5.25 V | 2.7 V to 5.25 V | 2.7 V to 5.25 V |
| Number of Channels | 1 | 1 | 1 | 1 | 1 | 1 |
| Operating Temperature | -40 °C to +85 °C | -40 °C to +85 °C | -40 °C to +85 °C | -40 °C to +85 °C | -40 °C to +85 °C | -40 °C to +85 °C |
主な差別化要因
- Highest sample rate in its voltage-supply and package class （vs ADC101S021CISDX)
- Lower cost vs 12-bit pin-compatible family （vs ADC121S101CISDX)
- Single-channel converter with deterministic SAR latency （vs Pipeline ADCs (e.g., ADS5270 family))
設計ノート
Decouple VDD (pin 3) with a 10 uF ceramic capacitor in parallel with a 0.1 uF X7R ceramic placed within 5 mm of the pin; the ADC101S101 draws sharp transient currents during the internal DAC switching events of each conversion cycle, and insufficient decoupling will inject digital switching noise into the analog input. Power the analog VDD from a low-noise LDO or filtered ferrite-bead isolation from noisy digital rails.
Keep the analog input trace (pin 1 CH0) short and guarded with a ground trace or a ground plane on either side. Use a low-impedance driver (op-amp output or low-Ron mux) to drive CH0; source impedances above 1 kΩ will degrade AC performance and increase conversion-to-conversion variation. Route SCLK and DOUT on the digital side of the PCB, away from the analog input, to minimize digital coupling into the input signal.
CS (pin 6) is also the power-down control: pulling CS high after a conversion powers down the part, reducing current consumption to sub-microamp levels. Do NOT leave CS floating - if the SPI master is not yet configured at boot, the floating CS may power up the ADC unpredictably. Tie CS to the MCU GPIO with a defined startup state, or to VDD via a 100 kΩ pull-up so the ADC defaults to power-down between conversions.
Source-terminate SCLK if the MCU-to-ADC distance is greater than ~50 mm (about 1.5 inches) to prevent ringing and double-clocking the SAR internal logic. A 33 Ω resistor in series with SCLK at the MCU pin, near the source, normally damps reflections without slowing the rise/fall times appreciably at 20 MHz. Keep SCLK traces short and matched in length to DOUT to minimize skew on the returned serial data.
コンプライアンス情報
RoHS compliant and lead-free per TI product page. The /NOPB suffix explicitly denotes Pb-free part labeling per TI convention. Halogen-free status not stated in available data.
