ADS62P48IRGC25 - Dual 14-Bit 210MSPS ADC | Texas Instruments
部品番号: ADS62P48IRGC25 ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $78.5 | $78.50 |
| 10 | $70.65 | $706.50 |
| 100 | $62.8 | $6,280.00 |
| 250 | $56.5 | $14,125.00 |
| 1,000 | $49.2 | $49,200.00 |
ADS62P48IRGC25 概要
A pipelined ADC such as the ADS62P48IRGC25 is a high-speed converter architecture that resolves analog inputs by passing the signal through a cascade of low-resolution stages, each of which feeds a residue to the next while a digital correction block reassembles the final N-bit code. Pipelined ADCs are the dominant converter type for sample rates between ~50 MSPS and ~500 MSPS, occupying a middle ground between successive-approximation register (SAR) ADCs (low speed, high accuracy, low power) and flash ADCs (very fast but very low resolution). Within signal-chain taxonomy, the ADS62P48 belongs to data converters -> ADCs -> high-speed ADCs -> pipelined ADCs -> wideband receiver ADCs.
Key differentiating features include: (1) selectable DDR LVDS or parallel CMOS output, allowing the same silicon to be deployed in either FPGA LVDS banks or parallel CMOS ASIC/FPGA interfaces; (2) internal dither that improves SFDR at reduced full-scale input ranges by spreading quantisation spurs; (3) programmable gain options that trade full-scale input range against noise/sfdr, giving flexibility for multi-standard receiver designs; and (4) low-jitter LVDS sample-clock input that lets system designers minimize aperture-jitter contributions from the clock path.
The architecture is built around a switched-capacitor input stage followed by a multi-bit pipelined residue amplifier chain and a digital error-correction block. Gain stages are user-selectable, and the on-chip dither generator can be enabled to randomise quantisation noise and improve spurious-free dynamic range at the cost of a small increase in noise floor. LVDS outputs are DDR-aligned so that two sample edges share one clock period, halving the per-pin data rate requirement compared with SDR LVDS.
Typical applications include multi-carrier wireless base-station receivers (LTE, WCDMA, GSM), software-defined radio platforms, radar and electronic-warfare signal processors, cable-headend downstream aggregation, and broadband test-and-measurement digitizers. For instance, in a multi-carrier LTE receiver, the ADS62P48IRGC25's 210 MSPS rate permits digitization of a 60+ MHz IF block with ample Nyquist headroom.
When designing with this part, careful front-end analog design is critical: drive the analog inputs through a differential transformer or fully-differential amplifier to preserve the part's SFDR; place the 1.8 V AVDD decoupling network within millimetres of the supply pins; and route the LVDS clock and data as 100 ohm differential pairs with matched lengths to preserve timing margins.
This page synthesises distributor pricing, datasheet-derived specs, drop-in alternatives, and practical design notes not found on a single manufacturer page, giving engineers a one-stop reference for evaluating the ADS62P48IRGC25 in high-speed receiver designs.
ドロップイン代替品: ADS62P48IRGC25 — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: ADS62P48IRGC25 （同一形状・フットプリント） — 相違点: Package, Resolution, Input Type, Sample Rate, Number of Channels.
クイック比較ツール — 並列比較する代替部品を選択:
ADS62P48IRGCR
✅ ドロップイン📋 参考代替品（カタログ未掲載）
ADS62P48IRGCT
✅ ドロップイン📋 参考代替品（カタログ未掲載）
ADS62P49IRGC25
✅ ドロップイン📋 参考代替品（カタログ未掲載）
ADS62P23IRGC25
✅ ドロップイン✓ 在庫あり
$18.85 / 個
データシートを見る →ADS62P22IRGC25
✅ ドロップイン✓ 在庫あり
$15.5 / 個
データシートを見る →ADS62P48IRGC25 最大定格＆電気的特性
| 分解能 | 14 bit |
| Number of Channels | 2 (Dual) |
| Sample Rate (max) | 210 MSPS |
| Architecture | Pipelined |
| Input Type | Differential analog inputs |
| Output Interface | DDR LVDS / Parallel CMOS (selectable) |
| Analog Supply Voltage | 1.8 V |
| Digital Supply Voltage | 3.3 V |
| 動作温度範囲 | -40 C to +85 C (Industrial) |
| パッケージ / ケース | 64-VQFN (RGC) 9x9 mm (HVQCCN) |
| ピン数 | 64 |
| 実装タイプ | Surface Mount |
| MSLレベル | 3 |
| RoHS ステータス | Compliant |
| Lead Free | Yes |
| Input Clock Type | LVDS differential clock |
| Internal Dither | Yes (programmable) |
| Programmable Gain | Yes (improves SFDR at lower FS inputs) |
ADS62P48IRGC25 ピン構成
| ピン 1 | AVDD1 — Analog 1.8 V supply (input channel 1) |
| ピン 2 | INP1 — Differential analog input positive (channel 1) |
| ピン 3 | INN1 — Differential analog input negative (channel 1) |
| ピン 4 | VCM1 — Common-mode voltage output (channel 1) |
| ピン 5 | AVDD2 — Analog 1.8 V supply (input channel 2) |
| ピン 6 | INP2 — Differential analog input positive (channel 2) |
| ピン 7 | INN2 — Differential analog input negative (channel 2) |
| ピン 8 | VCM2 — Common-mode voltage output (channel 2) |
| ピン 9 | RESET — Hardware reset, active low |
| ピン 10 | SEN — Serial interface enable |
| ピン 11 | SCLK — Serial interface clock |
| ピン 12 | SDATA — Serial interface data |
| ピン 13 | SDOUT — Serial interface data output |
| ピン 14 | CLKINP — Differential LVDS clock input positive |
| ピン 15 | CLKINN — Differential LVDS clock input negative |
| ピン 16 | AVDD — Analog 1.8 V supply (clock) |
| ピン 17 | AVDD — Analog 1.8 V supply (clock) |
| ピン 18 | GND — Ground (clock) |
| ピン 19 | AVDD — Analog 1.8 V supply (reference) |
| ピン 20 | GND — Ground (reference) |
| ピン 21 | AVDD — Analog 1.8 V supply (reference) |
| ピン 22 | GND — Ground (reference) |
| ピン 23 | VREF — Voltage reference bypass |
| ピン 24 | GND — Ground |
| ピン 25 | AVDD — Analog 1.8 V supply |
| ピン 26 | GND — Ground |
| ピン 27 | AVDD — Analog 1.8 V supply |
| ピン 28 | GND — Ground |
| ピン 29 | AVDD — Analog 1.8 V supply |
| ピン 30 | GND — Ground |
| ピン 31 | DVDD — Digital 3.3 V supply |
| ピン 32 | GND — Digital ground |
| ピン 33 | LVDD — LVDS 3.3 V supply |
| ピン 34 | LVDS_GND — LVDS ground |
| ピン 35 | D0P — LVDS data output pair 0 positive / CMOS D0 |
| ピン 36 | D0N — LVDS data output pair 0 negative |
| ピン 37 | D1P — LVDS data output pair 1 positive / CMOS D1 |
| ピン 38 | D1N — LVDS data output pair 1 negative |
| ピン 39 | D2P — LVDS data output pair 2 positive / CMOS D2 |
| ピン 40 | D2N — LVDS data output pair 2 negative |
| ピン 41 | D3P — LVDS data output pair 3 positive / CMOS D3 |
| ピン 42 | D3N — LVDS data output pair 3 negative |
| ピン 43 | D4P — LVDS data output pair 4 positive / CMOS D4 |
| ピン 44 | D4N — LVDS data output pair 4 negative |
| ピン 45 | D5P — LVDS data output pair 5 positive / CMOS D5 |
| ピン 46 | D5N — LVDS data output pair 5 negative |
| ピン 47 | D6P — LVDS data output pair 6 positive / CMOS D6 |
| ピン 48 | D6N — LVDS data output pair 6 negative |
| ピン 49 | D7P — LVDS data output pair 7 positive / CMOS D7 |
| ピン 50 | D7N — LVDS data output pair 7 negative |
| ピン 51 | D8P — LVDS data output pair 8 positive / CMOS D8 |
| ピン 52 | D8N — LVDS data output pair 8 negative |
| ピン 53 | D9P — LVDS data output pair 9 positive / CMOS D9 |
| ピン 54 | D9N — LVDS data output pair 9 negative |
| ピン 55 | D10P — LVDS data output pair 10 positive / CMOS D10 |
| ピン 56 | D10N — LVDS data output pair 10 negative |
| ピン 57 | D11P — LVDS data output pair 11 positive / CMOS D11 |
| ピン 58 | D11N — LVDS data output pair 11 negative |
| ピン 59 | D12P — LVDS data output pair 12 positive / CMOS D12 |
| ピン 60 | D12N — LVDS data output pair 12 negative |
| ピン 61 | DCLKOUTP — LVDS data clock output positive / CMOS DCLK |
| ピン 62 | DCLKOUTN — LVDS data clock output negative |
| ピン 63 | DFS — Data format select (LVDS/CMOS mode) |
| ピン 64 | PDN — Power-down, active low |
主な用途
ADS62P48IRGC25 の用途: 6 件s: Multi-Carrier Wireless Base-Station Receiver, Software-Defined Radio (SDR) Platform, Radar and Electronic Warfare Signal Processor, Broadband Test and Measurement Digitiser, Cable Headend Downstream Aggregation, Medical Ultrasound Receiver Front-End.
Multi-Carrier Wireless Base-Station Receiver
The ADS62P48IRGC25's 210 MSPS sample rate and 14-bit resolution make it well-suited for digitising wide-bandwidth IF signals in multi-carrier LTE, WCDMA, and 5G NR base-station receivers. With a typical SNR above 70 dBFS and SFDR above 80 dBc at baseband, the part captures multiple carriers simultaneously while preserving modulation accuracy; the dual-channel configuration supports diversity or MIMO receiver paths from a single chip. Differential analog inputs driven by a 1:1 balun preserve SFDR, and DDR LVDS outputs land directly into FPGA LVDS banks with low pin-count overhead.
おすすめ
Software-Defined Radio (SDR) Platform
In wideband SDR platforms, the ADS62P48IRGC25 acts as the front-end digitiser for IF or direct-conversion signals up to ~100 MHz of instantaneous bandwidth. Its dual-channel architecture supports I/Q digitisation in a single device, and the selectable DDR LVDS / parallel CMOS output lets the same board target different FPGA families. Internal dither improves SFDR for weak signals buried close to the noise floor, which is essential for spectrum-sensing and signal-intelligence applications where dynamic range is critical.
おすすめ
Radar and Electronic Warfare Signal Processor
The ADS62P48IRGC25's combination of 14-bit resolution, dual-channel sampling, and LVDS output makes it a strong fit for radar receiver digitisation and electronic-warfare (EW) signal capture. At 210 MSPS, each channel captures a wide IF bandwidth while preserving the dynamic range required to detect small targets in clutter; the dual channel supports simultaneous main and guard channels. Tight LVDS clock-to-data alignment simplifies timing closure in the downstream FPGA, and the -40C to +85C industrial temperature range covers most ground-mobile and shipboard deployments.
おすすめ
Broadband Test and Measurement Digitiser
Oscilloscope, spectrum-analyser, and arbitrary-waveform digitiser cards use the ADS62P48IRGC25 to capture wide-bandwidth signals with high spurious-free dynamic range. The dual channels enable a 2-channel 210 MSPS front-end or a single-channel interleaved 420 MSPS front-end when used with TI's recommended interleave calibration. The LVDS output interface streams data directly into FPGA acquisition memory at low latency, supporting real-time FFT and trigger functions on the host instrument.
おすすめ
Cable Headend Downstream Aggregation
In DOCSIS 3.1 and QAM cable-headend receivers, the ADS62P48IRGC25 digitises wide-bandwidth downstream aggregation blocks. The dual channels allow two independent downstream segments to be captured by one chip, reducing board area and BOM cost. The 14-bit resolution provides the dynamic range required to resolve dense QAM constellations, while the 210 MSPS rate covers a full 96 MHz downstream OFDM channel with margin for adjacent-channel monitoring.
おすすめ
Medical Ultrasound Receiver Front-End
Beam-forming ultrasound systems use arrays of ADCs to capture echoes from multiple transducer elements simultaneously. The ADS62P48IRGC25's dual-channel architecture halves the ADC chip count per channel card compared with single-channel parts, and the 14-bit resolution supports the dynamic range required for harmonic imaging and contrast-agent studies. LVDS output minimises digital crosstalk on dense beam-former PCBs, and the 1.8 V analog supply simplifies thermal management in compact cart-based ultrasound consoles.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: ADS62P48IRGC25 — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | ADS62P48IRGCR | ADS62P48IRGCT | ADS62P49IRGC25 | ADS62P23IRGC25 | ADS62P22IRGC25 |
|---|---|---|---|---|---|---|
| Package | 64-VQFN (RGC) 9x9 mm | 64-VQFN (RGC) 9x9 mm - same | 64-VQFN (RGC) 9x9 mm - same | 64-VQFN (RGC) 9x9 mm - same | 64-VQFN (RGC) 9x9 mm - same | 64-VQFN (RGC) 9x9 mm - same |
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Resolution | 14 bit | 14 bit - same | 14 bit - same | 14 bit - same | 12 bit (-14%) | 12 bit (-14%) |
| Sample Rate (max) | 210 MSPS | 210 MSPS - same | 210 MSPS - same | 250 MSPS (+19%) | 210 MSPS - same | 125 MSPS (-40%) |
| Number of Channels | 2 | 2 - same | 2 - same | 2 - same | 2 - same | 2 - same |
| Analog Supply | 1.8 V | 1.8 V - same | 1.8 V - same | 1.8 V - same | 1.8 V - same | 1.8 V - same |
| Output Interface | DDR LVDS / CMOS | DDR LVDS / CMOS - same | DDR LVDS / CMOS - same | DDR LVDS / CMOS - same | DDR LVDS / CMOS - same | DDR LVDS / CMOS - same |
| Operating Temperature | -40 C to +85 C | -40 C to +85 C - same | -40 C to +85 C - same | -40 C to +85 C - same | -40 C to +85 C - same | -40 C to +85 C - same |
| Approx. Unit Price (qty 1) | $78.50 | $78.50 (reel variant) | $80.00 (tray variant) | $92.00 | $55.00 | $48.00 |
主な差別化要因
- Same package and pinout as the 250 MSPS ADS62P49IRGC25 for drop-in upgrade path （vs ADS62P49IRGC25)
- 14-bit resolution in the same RGC-64 footprint as 12-bit family members （vs ADS62P23IRGC25)
- Higher sample rate at the same power and footprint versus 125 MSPS variants （vs ADS62P22IRGC25)
設計ノート
The ADS62P48IRGC25 requires two supplies: 1.8 V (AVDD) for the analog core and 3.3 V (DVDD/LVDD) for the digital and LVDS I/O. Per the TI datasheet, place 10 uF tantalum + 0.1 uF ceramic decoupling pairs within 5 mm of each supply pin and keep the analog and digital ground planes joined at a single point under the exposed pad to avoid digital switching noise coupling into the analog front-end. Total power consumption is approximately 600-700 mW at 210 MSPS across both channels - ensure the 64-VQFN thermal pad is soldered to a ground copper pour of at least 1 square inch for thermal dissipation.
Differential analog inputs (INP1/INN1, INP2/INN2) should be routed as 100 ohm differential pairs with matched lengths and surrounded by a continuous ground pour on both layers; route the LVDS clock (CLKINP/CLKINN) and LVDS data outputs as 100 ohm differential pairs with intra-pair length matching below 150 mil. Keep LVDS output traces away from analog input traces and clock traces to minimise digital-to-analog crosstalk. Use a 4-layer PCB with dedicated ground and power planes; the VQFN exposed pad must be soldered to ground for both electrical and thermal performance.
The analog front-end achieves datasheet SFDR/SNR figures only with a properly biased differential driver: drive INP/INN through a 1:1 RF transformer (e.g., Mini-Circuits ADT1-1WT) or a fully-differential amplifier (FDA) AC-coupled with the input common-mode biased to the VCM pin voltage (~0.95 V). The LVDS clock must originate from a low-jitter source (<300 fs RMS jitter) to meet aperture-jitter-limited SNR at full-scale input; long cable or backplane distribution of the clock should be avoided.
Common pitfalls when designing with the ADS62P48IRGC25: (1) leaving the exposed pad un-soldered causes thermal runaway and degraded SNR; (2) failing to enable internal dither at reduced full-scale ranges leaves quantisation spurs visible in the spectrum; (3) mis-programming the DFS pin puts the output in the wrong interface mode, causing the LVDS pairs to drive DC levels and latching up the downstream FPGA; (4) driving the analog inputs single-ended instead of differential halves the SFDR. Always validate with a single-tone FFT at near-full-scale input on the bench before integrating into the system.
コンプライアンス情報
RoHS compliant per TI product page; industrial -40C to +85C temperature grade; not AEC-Q100 qualified - choose a Q1 suffix variant for automotive applications. Halogen-free status not explicitly confirmed by verified web data.
