ADC12010CIVYX/NOPB - 12-Bit 10MSPS 160mW ADC | Texas Instruments
部品番号: ADC12010CIVYX/NOPB ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $9.85 | $9.85 |
| 10 | $8.91 | $89.10 |
| 100 | $7.62 | $762.00 |
| 500 | $6.55 | $3,275.00 |
| 1,000 | $5.48 | $5,480.00 |
ADC12010CIVYX/NOPB 概要
An ADC (Analog-to-Digital Converter) is an integrated circuit that samples continuous analog voltage levels and converts each sample into a discrete digital code; the result is a stream of binary numbers that a microcontroller, FPGA, or DSP can process. This particular device belongs to the pipelined ADC family, which sits between flash converters (fastest, lowest resolution) and sigma-delta ADCs (slowest, highest resolution). Within a digital system, the ADC bridges the analog physical world (sensors, transducers, RF front-ends) and the digital processing domain, making it part of the broader data-converter hierarchy (ADC -> data converter -> mixed-signal IC -> semiconductor).
Key electrical specifications include 12-bit resolution, ±0.3 LSB typical differential non-linearity (DNL), 11.3-bit typical effective number of bits (ENOB) at fIN = 10.1 MHz, and 2.4 V to 5 V compatible digital outputs that interface directly to modern logic families. The pipelined architecture combined with an internal sample-and-hold delivers low-latency conversion suitable for real-time acquisition, while an on-chip reference buffer simplifies external analog design by handling reference decoupling and drive requirements internally.
The ADC12010 shares pin compatibility with the ADC12020 (14-bit), ADC12040 (14-bit), ADC12L063 (12-bit), and ADC12L066 (12-bit) parts from Texas Instruments, allowing designers to upgrade resolution or sampling rate on an existing layout. Industrial temperature range (–40 °C to +85 °C), 32-LQFP footprint, and CMOS process technology make it suitable for cost-sensitive embedded designs that require a balance of speed, accuracy, and power.
Typical applications include portable and handheld test instruments, ultrasound baseband signal chains, CCD imaging front-ends, communications IF sampling, and low-latency process-control data acquisition. The 160 mW typical dissipation at full rate is well-suited for fan-less industrial enclosures; the power-down mode drops quiescent current for battery-powered portable measurement tools.
Designers should pay attention to PCB layout for the analog input network: use a wide ground plane, route the analog input as a 50 Ω controlled-impedance trace, and place the input RC anti-alias filter within 5 mm of the AIN pin to avoid aperture jitter degradation. Compared to higher-speed flash ADCs, the pipelined architecture introduces a fixed pipeline latency (typically 5–6 clock cycles at 10 MSPS) that must be accounted for in closed-loop control applications.
ドロップイン代替品: ADC12010CIVYX/NOPB — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
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ADC12010CIVY/NOPB
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ADC12020CIVYX/NOPB
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ADC12040CIVYX/NOPB
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ADC12L063CIVYX/NOPB
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ADC12L066CIVYX/NOPB
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ADC12010CIVYX/NOPB 最大定格＆電気的特性
| 分解能 | 12 bits |
| Conversion Rate (min) | 10 MSPS |
| Number of Analog Inputs | 1 |
| Architecture | Pipelined |
| Sample-and-Hold | Internal |
| Differential Nonlinearity (DNL) | ±0.3 LSB (typical) |
| Effective Number of Bits (ENOB) | 11.3 bits (typical at fIN = 10.1 MHz) |
| Data Interface | Parallel |
| Output Compatibility | 2.4 V to 5 V logic levels |
| Analog Supply Voltage | +5 V or ±5 V |
| Digital Supply Voltage | +5 V |
| Power Consumption (10 MHz) | 160 mW (typical) |
| Power Down Mode | Yes |
| On-Chip Reference Buffer | Yes |
| 動作温度 | -40 °C to +85 °C |
| パッケージ | 32-LQFP (NEY) 7 x 7 mm |
| 実装タイプ | Surface Mount |
| Packaging | Tape & Reel (TR) |
| Pin-to-Pin Compatible Family | ADC12020, ADC12040, ADC12L063, ADC12L066 |
| RoHS ステータス | Compliant |
ADC12010CIVYX/NOPB ピン構成
| ピン 1 | DVDD — Digital supply voltage (+5 V) |
| ピン 2 | DGND — Digital ground |
| ピン 3 | OE — Output enable (active high; tie high for normal operation) |
| ピン 4 | D0 — Data bit 0 (LSB), parallel output |
| ピン 5 | D1 — Data bit 1, parallel output |
| ピン 6 | D2 — Data bit 2, parallel output |
| ピン 7 | D3 — Data bit 3, parallel output |
| ピン 8 | D4 — Data bit 4, parallel output |
| ピン 9 | D5 — Data bit 5, parallel output |
| ピン 10 | D6 — Data bit 6, parallel output |
| ピン 11 | D7 — Data bit 7, parallel output |
| ピン 12 | D8 — Data bit 8, parallel output |
| ピン 13 | D9 — Data bit 9, parallel output |
| ピン 14 | D10 — Data bit 10, parallel output |
| ピン 15 | D11 — Data bit 11 (MSB), parallel output |
| ピン 16 | DGND — Digital ground |
| ピン 17 | CLK — Conversion clock input |
| ピン 18 | PD — Power down (active high) |
| ピン 19 | AGND — Analog ground |
| ピン 20 | AVDD — Analog supply voltage (+5 V) |
| ピン 21 | VREF — Voltage reference (internal buffer output) |
| ピン 22 | VREFIN — External reference voltage input |
| ピン 23 | AGND — Analog ground |
| ピン 24 | AIN — Analog input |
| ピン 25 | NC — Not connected (per datasheet) |
| ピン 26 | NC — Not connected (per datasheet) |
| ピン 27 | NC — Not connected (per datasheet) |
| ピン 28 | AVSS — Analog negative supply (for ±5 V operation); connect to AGND for single +5 V operation |
| ピン 29 | AVDD — Analog supply voltage (+5 V) |
| ピン 30 | AGND — Analog ground |
| ピン 31 | AGND — Analog ground |
| ピン 32 | DVDD — Digital supply voltage (+5 V) |
主な用途
ADC12010CIVYX/NOPB の用途: 6 件s: Portable Test and Measurement Instruments, Medical Ultrasound Baseband Signal Chain, Communications IF Sampling, CCD Imaging Sensor Digitization, Industrial Process Control Data Acquisition, Automotive Sensor Interface Modules.
Portable Test and Measurement Instruments
The TI ADC12010CIVYX/NOPB fits handheld digital oscilloscopes, bench-top DMMs, and portable logic-analyzer front-ends where 12-bit resolution at 10 MSPS offers sufficient bandwidth and dynamic range. The 160 mW typical power dissipation simplifies fan-less thermal design in compact enclosures, while the power-down mode drops quiescent current during standby duty cycles. The 32-LQFP (NEY) footprint supports standard 4-layer reflow assembly, and on-chip reference buffer eliminates a precision external reference on the BOM. Designers get 11.3-bit ENOB at fIN = 10.1 MHz which covers most mid-bandwidth signal acquisition scenarios. Compared with sigma-delta alternatives at this bandwidth, the pipelined architecture provides much lower latency, critical for triggering and transient capture.
おすすめ
Medical Ultrasound Baseband Signal Chain
The ADC12010CIVYX/NOPB is suitable for ultrasound baseband digitization after time-gain-control (TGC) amplification, where 10 MSPS captures typical mid-frequency diagnostic ultrasound bandwidth. Per the TI datasheet, ENOB of 11.3 bits at 10.1 MHz input supports the ~70 dB dynamic range needed for B-mode imaging after TGC compression. The industrial –40 °C to +85 °C temperature range and 160 mW dissipation accommodate portable probe designs that must remain patient-safe with low heating. Pin compatibility with the ADC12L063/066 lets designers trade resolution for power in different probe categories. The parallel digital interface simplifies DMA into FPGAs that handle beamforming across multiple channels.
おすすめ
Communications IF Sampling
In digital-IF receiver designs, the TI ADC12010CIVYX/NOPB digitizes intermediate-frequency signals in the 5-10 MHz range for software-defined-radio baseband processing. Its 12-bit resolution at 10 MSPS provides adequate headroom for narrowband demodulation with 70+ dB SFDR, while the pipelined architecture keeps conversion latency deterministic - critical for synchronization in burst-mode receivers. The internal sample-and-hold reduces external component count, and the 2.4 V to 5 V output compatibility interfaces directly to modern FPGAs without level shifting. Power dissipation of 160 mW is acceptable for fixed installations; battery-powered SDR adapters should evaluate the ADC12L063/066 lower-power members of the same pin-compatible family.
おすすめ
CCD Imaging Sensor Digitization
The TI ADC12010CIVYX/NOPB digitizes analog pixel data from CCD line-scan and area-array image sensors in industrial cameras and document scanners. Its 12-bit resolution captures the full grayscale range of typical CCD outputs, and the 10 MSPS throughput supports VGA-class frame rates after channel multiplexing. The parallel data interface feeds directly into video processing ASICs or FPGAs, while the on-chip reference buffer simplifies PCB layout in densely-populated camera modules. Operating from –40 °C to +85 °C suits outdoor machine-vision installations. Designers integrating multiple CCD channels can share a common clock distribution and use the power-down mode to disable unused ADC channels.
おすすめ
Industrial Process Control Data Acquisition
The TI ADC12010CIVYX/NOPB serves multi-channel data-acquisition systems in PLCs, process controllers, and industrial instrumentation where 12-bit resolution is sufficient for transducer signal conditioning. The parallel interface enables deterministic real-time sampling for closed-loop control, while the pipelined architecture provides predictable conversion latency that simplifies loop-timing analysis. The 32-LQFP (NEY) industrial-grade package withstands factory-floor thermal and vibration environments, and the on-chip reference buffer reduces BOM count and manufacturing test cost. Power dissipation of 160 mW at 10 MSPS keeps thermal design simple for sealed IP65 enclosures common in process plants.
おすすめ
Automotive Sensor Interface Modules
The TI ADC12010CIVYX/NOPB digitizes analog signals from automotive sensors (pressure, position, temperature) in body and chassis ECUs that do not require AEC-Q100 qualification. The industrial –40 °C to +85 °C operating range covers most cabin and under-hood applications, while the 12-bit resolution and 10 MSPS throughput comfortably handle multi-axis inertial sensor arrays. The pipelined architecture keeps control-loop latency low, important for active suspension and steering systems. For safety-critical ADAS sensors requiring AEC-Q100, designers should evaluate the ADC12020/040-Q1 automotive-qualified variants from the same family.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: ADC12010CIVYX/NOPB — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | ADC12010CIVY/NOPB | ADC12020CIVYX/NOPB | ADC12040CIVYX/NOPB | ADC12L063CIVYX/NOPB | ADC12L066CIVYX/NOPB |
|---|---|---|---|---|---|---|
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Package | 32-LQFP (NEY) 7x7 mm | 32-LQFP (NEY) 7x7 mm - same | 32-LQFP (NEY) 7x7 mm - same | 32-LQFP (NEY) 7x7 mm - same | 32-LQFP (NEY) 7x7 mm - same | 32-LQFP (NEY) 7x7 mm - same |
| Resolution | 12 bits | 12 bits | 14 bits | 14 bits | 12 bits | 12 bits |
| Sampling Rate (MSPS) | 10 MSPS | 10 MSPS | 10 MSPS | 40 MSPS | 10 MSPS (low power) | 10 MSPS (low power) |
| Architecture | Pipelined with internal S/H | Pipelined with internal S/H | Pipelined with internal S/H | Pipelined with internal S/H | Pipelined with internal S/H | Pipelined with internal S/H |
| Operating Temperature | -40 °C to +85 °C | -40 °C to +85 °C | -40 °C to +85 °C | -40 °C to +85 °C | -40 °C to +85 °C | -40 °C to +85 °C |
| Data Interface | Parallel (12-bit) | Parallel (12-bit) | Parallel (14-bit) | Parallel (14-bit) | Parallel (12-bit) | Parallel (12-bit) |
主な差別化要因
- Pin-compatible resolution upgrade path within same TI family （vs ADC12020CIVYX/NOPB (14-bit) and ADC12040CIVYX/NOPB (14-bit, 40 MSPS))
- Lower-power pin-compatible variants in same package （vs ADC12L063CIVYX/NOPB and ADC12L066CIVYX/NOPB (12-bit low-power variants))
- Tape-and-reel packaging for high-volume SMT production （vs ADC12010CIVY/NOPB (tray variant of same die))
設計ノート
Place the analog input anti-alias RC filter (typically 50 Ω series resistor with 10 pF to 33 pF shunt capacitor) within 5 mm of the AIN pin to avoid aperture jitter degradation. Use a continuous analog ground plane under the ADC and avoid routing digital return currents through it; the AGND and DGND pins should connect at a single point near the ADC. The VREF decoupling capacitor should be placed as close as possible to the VREF pin with a 0.1 µF ceramic plus 10 µF tantalum in parallel for low-frequency noise suppression. Keep digital output traces (D0-D11) routed together with matched length (±2 mm) to minimize skew when sampling at 10 MSPS into an FPGA.
Estimated: At analog supply +5 V and a typical 160 mW consumption, the AVDD pin draws approximately 32 mA (with proportional split if using ±5 V). Use a low-noise LDO such as TPS7A4701 for the analog AVDD rail and a separate regulator for DVDD to prevent digital switching noise from coupling into the analog input. Decoupling should be 0.1 µF ceramic right at each AVDD/DVDD pin plus a 10 µF bulk capacitor near the regulator output. The PD (power-down) pin allows disabling the ADC to drop quiescent current; do not leave PD floating - tie it low through a 10 kΩ resistor to DVDD for normal operation.
Estimated: Pipelined ADCs introduce a fixed latency of approximately 5–6 clock cycles at 10 MSPS. In closed-loop control applications where latency matters, account for this delay in the control algorithm. The OE (output enable) pin controls the tri-state state of the digital outputs; tie OE high for normal operation and use it to bus-share multiple ADCs on a single parallel data bus - but never connect two ADC outputs simultaneously without OE coordination. For ±5 V analog supply operation, the AVSS pin must be connected to -5 V (not AGND); misuse causes input range compression and possible damage. The internal reference buffer simplifies design but introduces a reference warm-up time of approximately 100 µs after power-up - delay CLK application until after this settling period for accurate conversions.
コンプライアンス情報
RoHS and lead-free per TI product page (NOPB suffix indicates no Pb). Industrial temperature grade only (-40°C to +85°C); not AEC-Q100 qualified - designers needing automotive qualification should evaluate ADC12020/040-Q1 variants.
