ADC124S021CIMM - 4-Ch 12-Bit 50-200 kSPS SAR ADC | Texas Instruments
部品番号: ADC124S021CIMM ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $6.42 | $6.42 |
| 10 | $5.94 | $59.40 |
| 100 | $5.18 | $518.00 |
| 500 | $4.42 | $2,210.00 |
| 1,000 | $3.78 | $3,780.00 |
ADC124S021CIMM 概要
An ADC (analog-to-digital converter) is an integrated circuit that converts continuous analog voltages into discrete digital codes. Within the data-converter hierarchy, SAR ADCs use a binary-search algorithm with a high-speed comparator and a switched-capacitor DAC to achieve deterministic latency and excellent DC accuracy without pipeline delay, making them the preferred architecture for multiplexed multi-channel data acquisition, precision measurement, and motor/encoder feedback.
Key features of the ADC124S021 include four single-ended input channels multiplexed into a shared track/hold, an SPI/QSPI/MICROWIRE-compatible serial interface, true-differential inputs on each channel pair via pseudo-differential sampling, ±1 LSB INL (max), DNL (no missing codes), and a low 2.3 mA (typical at 3 V) supply current that drops with reduced throughput. The wide supply range allows direct connection to 3.3 V microcontrollers without level shifters.
Internally, the device uses a charge-distribution SAR core with on-chip track/hold and an internal reference structure that supports both internal 2.5 V (4.5 V supply) reference modes and an external reference mode. This flexibility allows designers to trade noise, absolute accuracy, and channel count against PCB simplicity. The architecture guarantees zero pipeline latency, which simplifies event-driven sampling and closed-loop control.
Typical applications include multi-channel data-acquisition systems, industrial process control, portable instrumentation, battery monitoring, optical sensor front-ends, and embedded system analog expansion. Any design that needs to digitize 2 to 4 sensors with good DC accuracy and modest speed is a strong fit.
A key design consideration is decoupling: place a 0.1 µF ceramic bypass capacitor within 5 mm of the VDD pin and a 10 µF bulk capacitor on the supply rail. Route analog and digital grounds on a split plane with a single-point tie beneath the IC. Verify that the SPI clock idles low (CPOL = 1, CPHA = 0) to match the ADC124S021's timing.
This page synthesizes distributor pricing, validated drop-in alternatives (same-brand TI family first, then cross-brand parts from the verified web data), and practical layout guidance not found in the manufacturer datasheet alone.
ドロップイン代替品: ADC124S021CIMM — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: ADC124S021CIMM （同一形状・フットプリント） — 相違点: Package, Architecture, Number of Channels, Digital Interface, RoHS Status.
クイック比較ツール — 並列比較する代替部品を選択:
ADC124S021CIMM/NOPB
✅ ドロップイン📋 参考代替品（カタログ未掲載）
ADC122S021CIMMX
✅ ドロップイン✓ 在庫あり
$2.35 / 個
データシートを見る →ADC124S101CIMM
✅ ドロップイン📋 参考代替品（カタログ未掲載）
ADC124S021CIMMX
✅ ドロップイン✓ 在庫あり
$2.07 / 個
データシートを見る →ADC122S101CIMM
✅ ドロップイン✓ 在庫あり
$1.96 / 個
データシートを見る →ADC124S051CIMM
✅ ドロップイン✓ 在庫あり
$4.05 / 個
データシートを見る →ADC124S021CISD
✅ ドロップイン📋 参考代替品（カタログ未掲載）
ADC124S021CIMM 最大定格＆電気的特性
| Manufacturer | National Semiconductor (now Texas Instruments) |
| Part Number | ADC124S021CIMM |
| Suffix (NOPB) | Lead-free, Pb-free (separate order code ADC124S021CIMM/NOPB) |
| 分解能 | 12 bits |
| Number of Channels | 4 (single-ended) |
| Architecture | SAR (Successive Approximation Register) |
| Sample Rate | 50 ksps to 200 ksps |
| Supply Voltage (VDD) | 2.7 V to 5.25 V |
| 電源電流 | 2.3 mA typical at 3 V, 200 kSPS |
| Input Type | Single-ended, unipolar; pseudo-differential mode via CHn/CHn+1 pairing |
| Analog Input Range | 0 V to VREF (or 0 V to VDD in internal-reference mode) |
| INL（積分非直線性） | ±1 LSB (max) |
| DNL (Differential Nonlinearity) | ±1 LSB (max, no missing codes) |
| 基準電圧 | Internal 2.5 V (on 4.5 V to 5.25 V supply) or external VREF input |
| Digital Interface | SPI, MICROWIRE-compatible, mode 1 (CPOL=1, CPHA=0) |
| パッケージ | 10-pin VSSOP / MSOP (TI DGS, NSC P0MUB10A) |
| 動作温度範囲 | -40 °C to +85 °C (industrial) |
| 実装タイプ | Surface Mount |
| RoHS ステータス | Compliant (lead-free via /NOPB) |
ADC124S021CIMM ピン構成
| ピン 1 | CH0 — Analog input channel 0 |
| ピン 2 | CH1 — Analog input channel 1 |
| ピン 3 | CH2 — Analog input channel 2 |
| ピン 4 | CH3 — Analog input channel 3 |
| ピン 5 | GND — Ground (analog and digital common) |
| ピン 6 | VDD — Digital supply voltage (2.7 V to 5.25 V) |
| ピン 7 | DOUT — Serial data output (SPI) |
| ピン 8 | DIN — Serial data input (SPI, ties to DOUT in daisy-chain) |
| ピン 9 | SCLK — Serial clock input (CPOL=1, CPHA=0) |
| ピン 10 | CS — Chip-select (active LOW) |
主な用途
ADC124S021CIMM の用途: 6 件s: Industrial Multi-Sensor Monitoring, Battery-Powered Portable Instrumentation, Optical Sensor Front-Ends (Photodiode / Color / IR), Embedded Analog Expansion for Microcontrollers, Motor Control / Encoder Feedback, Data Acquisition Modules (PLC / 4-20 mA Sensing).
Industrial Multi-Sensor Monitoring
The ADC124S021CIMM's 4 single-ended channels and 50-200 ksps sample rate make it well-suited for digitizing multiple analog sensors in industrial monitoring systems - temperature via RTD, pressure via bridge, flow via 4-20 mA sense resistor, and humidity via analog front-end. The internal SAR core delivers ±1 LSB INL/DNL with no missing codes at up to 200 ksps, which is more than adequate for industrial signals whose bandwidth rarely exceeds 10 kHz. Place a 0.1 µF ceramic bypass within 5 mm of VDD and route analog/digital grounds with a single-point tie beneath the IC to keep switching noise out of the measurement chain. The 2.7-5.25 V supply directly accepts 3.3 V or 5 V rail power without level shifters.
おすすめ
Battery-Powered Portable Instrumentation
The ADC124S021CIMM's 2.3 mA typical supply current and single 2.7-5.25 V supply directly accept a single-cell Li-ion or 3 V coin-cell rail, making it a strong fit for handheld multimeters, portable gas analyzers, and field data loggers. The wide 50 ksps to 200 ksps range lets you reduce the effective sample rate during low-power standby - SAR ADCs scale consumption with throughput, so a 1 kSPS update rate draws less than a 200 kSPS rate. The 12-bit resolution is sufficient for sensor-front-end measurements with 0.024% resolution (FS = 3.3 V → 806 µV per LSB). Choose the internal 2.5 V reference mode at VDD = 5 V to eliminate an external reference and save board space.
おすすめ
Optical Sensor Front-Ends (Photodiode / Color / IR)
In optical sensor systems (photodiodes, colorimeters, ambient-light sensors, IR receivers), the ADC124S021CIMM digitizes multiple photodiode current-to-voltage outputs after a transimpedance stage. With four input channels, a single chip handles RGB color sensing plus ambient-light compensation in one device, replacing three or four discrete ADCs. The SAR architecture's inherent single-shot conversion makes it ideal for shutter-controlled or sample-and-hold optical measurements, where deterministic latency is critical. The pseudo-differential mode (CHn/CHn+1 paired) lets you ground-reference cancel common-mode noise from a noisy environment.
おすすめ
Embedded Analog Expansion for Microcontrollers
Many low-cost microcontrollers (Cortex-M0+/PIC16) lack analog inputs or have only 8-10-bit ADCs, making the ADC124S021CIMM an ideal external analog front-end. The SPI mode-1 interface (CPOL=1, CPHA=0) is supported by virtually every MCU's hardware SPI peripheral, and the 4-channel multiplexed input lets one SPI device add four 12-bit conversions to a system that previously had none. The 200 ksps ceiling is more than adequate for slowly varying control signals (temperature, pressure, position, voltage monitoring). The 10-pin VSSOP package fits beside even the smallest 8-pin SOIC MCUs.
おすすめ
Motor Control / Encoder Feedback
In BLDC and stepper motor drives, the ADC124S021CIMM can sample phase current (via current-sense resistor + op-amp), back-EMF voltage, potentiometer position, and temperature from a single chip. The SAR ADC's deterministic zero-latency conversion is critical for current-sensing in FOC motor-control loops - you cannot tolerate the 3-5 cycle pipeline delay of a pipelined ADC. The 50-200 ksps range covers up to 4 phase-current samples per PWM period at 50 kHz PWM, sufficient for sub-1 kHz electrical frequencies. Use the internal 2.5 V reference (5 V supply mode) to keep BOM minimal.
おすすめ
Data Acquisition Modules (PLC / 4-20 mA Sensing)
Process-control and PLC analog input modules typically digitize 4-20 mA loops for temperature, flow, pressure, or position. The ADC124S021CIMM handles four isolated (or non-isolated) 4-20 mA inputs after a 250 Ω sense resistor converts current to voltage (1-5 V). At 12 bits over 4 V span, each LSB is ~977 µV (~6.25 µA), giving ~0.04% resolution adequate for 12-bit process-control modules. The wide 2.7-5.25 V supply allows the same part to power from 3.3 V or 24 V (post-regulator) PLC rails. The industrial -40 °C to +85 °C operating range is ideal for factory-floor deployments.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: ADC124S021CIMM — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | ADC124S021CIMM/NOPB | ADC122S021CIMM | ADC124S101CIMM | ADC124S051CIMM | ADC122S101CIMM |
|---|---|---|---|---|---|---|
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Package | VSSOP-10 (DGS) | VSSOP-10 (DGS) - same | VSSOP-10 (DGS) - same | VSSOP-10 (DGS) - same | VSSOP-10 (DGS) - same | VSSOP-10 (DGS) - same |
| Resolution | 12 bits | 12 bits | 12 bits | 12 bits | 12 bits | 12 bits |
| Number of Channels | 4 | 4 | 2 (50% fewer) | 4 | 4 | 2 (50% fewer) |
| Sample Rate | 50-200 ksps | 50-200 ksps (same) | 50-200 ksps (same) | 50-500 ksps (+150%) | 50-500 ksps (+150%) | 50-500 ksps (+150%) |
| Supply Voltage | 2.7 V to 5.25 V | 2.7 V to 5.25 V | 2.7 V to 5.25 V | 2.7 V to 5.25 V | 2.7 V to 5.25 V | 2.7 V to 5.25 V |
| Interface Mode | Mode 1 (CPOL=1, CPHA=0) | Mode 1 (same) | Mode 1 (same) | Mode 1 (same) | Mode 1 (same) | Mode 1 (same) |
| RoHS Compliance | Lead-finish version (non-NOPB); NOPB variant is RoHS-compliant | RoHS-compliant (Pb-free) | Lead-finish; /NOPB variant RoHS-compliant | RoHS-compliant (modern order codes) | RoHS-compliant (modern order codes) | RoHS-compliant (modern order codes) |
| Operating Temperature | -40 °C to +85 °C | -40 °C to +85 °C | -40 °C to +85 °C | -40 °C to +85 °C | -40 °C to +85 °C | -40 °C to +85 °C |
主な差別化要因
- Wide specified sample-rate range (50-200 ksps) with full AC specs （vs ADC124S021CIMM/NOPB)
- Two more channels than ADC122S021 in same package （vs ADC122S021CIMM)
- Same pinout as faster 500 ksps ADC124S101CIMM （vs ADC124S101CIMM)
設計ノート
Place a 0.1 µF X7R ceramic decoupling capacitor within 5 mm of the VDD pin (pin 6) with the trace between the cap and the IC pin kept as short and wide as possible. Add a 10 µF bulk tantalum or ceramic on the VDD rail for low-frequency supply ripple. Split the ground plane into separate analog and digital regions with the tie-point located beneath the IC at pin 5 (GND); this minimizes the blocking time a digital return current couples into the analog ground. Route analog inputs (CH0-CH3) away from the SCLK/DOUT/CS traces to avoid capacitive coupling of digital edges into the analog signal chain.
The ADC124S021 uses SPI mode 1 (CPOL=1, CPHA=0) - SCLK idles HIGH and is clocked on the falling edge by the host MCU, with the ADC updating DOUT on the rising edge of SCLK. Misconfiguring the SPI peripheral (mode 0 / mode 3) is the most common reason for receiving all-1s or all-0s in the conversion result. Second common pitfall: not adding a small RC filter (1 kΩ + 100 pF) on analog inputs in the presence of multiplexer or relay switching transients, which can latch the input sample capacitor into an unsettled state.
Supply current at 200 kSPS with VDD = 3 V is approximately 2.3 mA typical. Lower sample rates reduce consumption linearly: at 50 kSPS, expect approximately 0.6-0.8 mA. In portable applications where the ADC samples only intermittently, power can be saved by gating SCLK (when CS is de-asserted, the ADC enters a low-power state). The internal 2.5 V reference mode requires VDD between 4.5 V and 5.25 V; below this, use an external reference on VREF to avoid degraded absolute accuracy.
For multi-channel scanning, allow at least 3 SCLK cycles after CS assertion before clocking the first conversion - this enables the analog input multiplexer and track-and-hold to settle to ±0.5 LSB. The maximum SCLK frequency is 3.2 MHz at VDD = 5 V (slower at lower VDD); exceeding this violates the SCLK-to-data-output timing (tD) and produces bit-shifted conversions. Terminate SCLK with a 33 Ω series resistor if the MCU-to-ADC trace exceeds 50 mm, to dampen reflections from the lumped capacitance of the input pin.
コンプライアンス情報
ADC124S021CIMM (lead-finish) is NOT RoHS-compliant - choose ADC124S021CIMM/NOPB for RoHS. REACH and conflict-minerals compliance status inherited from TI product family declarations. Not AEC-Q100 qualified (not automotive grade).
