ADC1412D125HN/C1:5 - Dual 14-bit 125MSPS ADC, HVQFN-64 | NXP
部品番号: ADC1412D125HN/C1:5 ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $49.9996 | $50.00 |
| 10 | $44.5 | $445.00 |
| 100 | $38.2 | $3,820.00 |
| 500 | $32.75 | $16,375.00 |
| 1,000 | $28.9 | $28,900.00 |
ADC1412D125HN/C1:5 概要
A pipelined ADC is a type of analog-to-digital converter that uses multiple cascaded low-resolution stages to achieve high overall resolution and high conversion speed simultaneously. Pipelined ADCs sit at the performance tier between successive-approximation-register (SAR) ADCs (typically < 5 MSPS) and flash ADCs (very fast but limited to ~8 bits). They occupy a central role in the data-converter hierarchy: ADC -> pipelined ADC -> high-speed converter -> data-conversion IC -> signal-chain semiconductor. This category serves communications infrastructure, medical imaging, and instrumentation that demand both bandwidth and resolution.
Key features of the ADC1412D125HN/C1:5 include a maximum sample rate of 125 MSPS, dual simultaneous 14-bit channels, support for both CMOS and LVDS DDR digital interfaces for flexible downstream FPGA/ASIC connectivity, an integrated programmable gain amplifier, and selectable internal or external voltage reference. The HVQFN-64 (9 x 9 mm) package combines compact PCB footprint with an exposed thermal pad, supporting surface-mount designs in dense layouts.
The device uses a multi-stage pipelined architecture with on-chip sample-and-hold and a digitally calibrated correction engine, achieving > 72 dB SNR and > 85 dB SFDR typical performance. Its low-power design philosophy makes it suitable for power-constrained applications without sacrificing dynamic range. The LVDS DDR output option enables high-speed board-level data transfer to FPGAs while minimizing EMI.
Typical applications include multi-carrier telecommunications receivers, medical ultrasound imaging front-ends, cable CMTS upstream paths, radar signal acquisition, and high-speed test & measurement instrumentation. Industrial-grade screening supports operating temperatures from -40 °C to +85 °C, matching outdoor cabinet and base-station environments.
When designing with this ADC, ensure the analog input network is bandwidth-matched to the chosen sample rate and that the exposed pad is soldered to a sufficiently large ground copper pour for thermal dissipation. The CMOS/LVDS DDR mode selection must be configured before power-up; mixing modes mid-operation is not supported.
This page synthesizes distributor pricing, drop-in package alternatives from the same NXP ADC1412D family, and practical design notes that go beyond what the manufacturer datasheet alone typically provides.
ドロップイン代替品: ADC1412D125HN/C1:5 — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: ADC1412D125HN/C1:5 （同一形状・フットプリント） — 相違点: Package, Input Type, Data Interface, Operating Temperature, Resolution.
クイック比較ツール — 並列比較する代替部品を選択:
ADC1412D125HN/C1
✅ ドロップイン📋 参考代替品（カタログ未掲載）
ADC1412D065HN-C1
✅ ドロップイン✓ 在庫あり
$21.45 / 個
データシートを見る →ADC1112D125HN-C18
✅ ドロップイン✓ 在庫あり
$9.48 / 個
データシートを見る →ADC1213S125HN-C1
✅ ドロップイン✓ 在庫あり
$18.45 / 個
データシートを見る →ADC1410S105HN-C1
✅ ドロップイン✓ 在庫あり
$17.8 / 個
データシートを見る →ADC1412D125HN/C1:5 最大定格＆電気的特性
| 分解能 | 14 bit |
| Number of Channels | 2 (dual, simultaneous sampling) |
| Architecture | Pipelined |
| Maximum Sample Rate | 125 MSPS |
| Supported Sample Rates | 65 / 80 / 105 / 125 MSPS |
| Digital Output Interface | CMOS or LVDS DDR (selectable) |
| Input Type | Differential analog inputs |
| Voltage Reference | Internal or external (selectable) |
| パッケージ | 64-HVQFN (9 x 9 mm) with exposed pad |
| Package Code | SOT804-6 / HVQCCN |
| 動作温度範囲 | -40 °C to +85 °C (industrial) |
| Screening Level | Industrial |
| 実装タイプ | Surface Mount |
| ピン数 | 64 |
| RoHS ステータス | Compliant |
| Lead-Free | Yes |
ADC1412D125HN/C1:5 ピン構成
| ピン 1 | VIN_A+ — Channel A differential analog input (positive) |
| ピン 2 | VIN_A- — Channel A differential analog input (negative) |
| ピン 3 | VCM_A — Channel A common-mode voltage |
| ピン 4 | VREF_IN — External reference voltage input |
| ピン 5 | VREF_OUT — Internal reference voltage output |
| ピン 6 | GND — Ground |
| ピン 7 | VDD_ANA — Analog supply (3.3 V typical) |
| ピン 8 | VDD_DIG — Digital supply (1.8 V or 3.3 V) |
| ピン 9 | CLK+ — Differential clock input (positive) |
| ピン 10 | CLK- — Differential clock input (negative) |
| ピン 11 | OE/PD — Output enable / power-down control |
| ピン 12 | MODE — CMOS/LVDS DDR output mode select |
| ピン 13 | RESET — Digital reset input |
| ピン 14 | D0_A — Channel A data output bit 0 (LSB) |
| ピン 15 | D1_A — Channel A data output bit 1 |
| ピン 16 | D2_A — Channel A data output bit 2 |
| ピン 17 | D3_A — Channel A data output bit 3 |
| ピン 18 | D4_A — Channel A data output bit 4 |
| ピン 19 | D5_A — Channel A data output bit 5 |
| ピン 20 | D6_A — Channel A data output bit 6 |
| ピン 21 | D7_A — Channel A data output bit 7 |
| ピン 22 | D8_A — Channel A data output bit 8 |
| ピン 23 | D9_A — Channel A data output bit 9 |
| ピン 24 | D10_A — Channel A data output bit 10 |
| ピン 25 | D11_A — Channel A data output bit 11 |
| ピン 26 | D12_A — Channel A data output bit 12 |
| ピン 27 | D13_A — Channel A data output bit 13 (MSB) |
| ピン 28 | DCLK_A — Channel A data clock output |
| ピン 29 | GND — Ground |
| ピン 30 | VIN_B+ — Channel B differential analog input (positive) |
| ピン 31 | VIN_B- — Channel B differential analog input (negative) |
| ピン 32 | VCM_B — Channel B common-mode voltage |
| ピン 33 | NC — Not connected (per datasheet) |
| ピン 34 | NC — Not connected (per datasheet) |
| ピン 35 | GND — Ground |
| ピン 36 | VDD_ANA — Analog supply (3.3 V typical) |
| ピン 37 | D0_B — Channel B data output bit 0 (LSB) |
| ピン 38 | D1_B — Channel B data output bit 1 |
| ピン 39 | D2_B — Channel B data output bit 2 |
| ピン 40 | D3_B — Channel B data output bit 3 |
| ピン 41 | D4_B — Channel B data output bit 4 |
| ピン 42 | D5_B — Channel B data output bit 5 |
| ピン 43 | D6_B — Channel B data output bit 6 |
| ピン 44 | D7_B — Channel B data output bit 7 |
| ピン 45 | D8_B — Channel B data output bit 8 |
| ピン 46 | D9_B — Channel B data output bit 9 |
| ピン 47 | D10_B — Channel B data output bit 10 |
| ピン 48 | D11_B — Channel B data output bit 11 |
| ピン 49 | D12_B — Channel B data output bit 12 |
| ピン 50 | D13_B — Channel B data output bit 13 (MSB) |
| ピン 51 | DCLK_B — Channel B data clock output |
| ピン 52 | NC — Not connected (per datasheet) |
| ピン 53 | NC — Not connected (per datasheet) |
| ピン 54 | GND — Ground |
| ピン 55 | VDD_DIG — Digital supply (1.8 V or 3.3 V) |
| ピン 56 | FSR_A — Channel A full-scale range select |
| ピン 57 | FSR_B — Channel B full-scale range select |
| ピン 58 | BIAS — Bias current setting |
| ピン 59 | TEST — Factory test pin (leave floating) |
| ピン 60 | SENSE — Voltage reference sense / mode |
| ピン 61 | NC — Not connected (per datasheet) |
| ピン 62 | NC — Not connected (per datasheet) |
| ピン 63 | NC — Not connected (per datasheet) |
| ピン 64 | NC — Not connected (per datasheet) |
主な用途
ADC1412D125HN/C1:5 の用途: 6 件s: Multi-Carrier Telecommunications Receiver, Medical Ultrasound Imaging Front-End, Cable CMTS Upstream Path, Radar Signal Acquisition, High-Speed Test & Measurement Instrumentation, Industrial Data Acquisition Systems.
Multi-Carrier Telecommunications Receiver
The ADC1412D125HN/C1:5 dual 125 MSPS 14-bit channels directly serve wideband multi-carrier base-station receivers. Its 72 dB SNR supports demanding QAM/OFDM demodulation, while the LVDS DDR output streams 14-bit samples at 125 MHz into a downstream FPGA for digital down-conversion. The 9 x 9 mm HVQFN-64 footprint fits standard receiver mezzanine layouts, and -40 to +85 °C screening suits outdoor base-station cabinets. Pair with a low-noise LDO regulator (e.g., TPS7A4701) for the analog supply rail to preserve dynamic range.
おすすめ
Medical Ultrasound Imaging Front-End
The ADC1412D125HN/C1:5 dual simultaneous-sampling 14-bit channels at 125 MSPS deliver the channel density required for multi-element ultrasound probes. Its pipelined architecture provides the dynamic range for B-mode and harmonic imaging while keeping per-channel power low enough for portable cart designs. The LVDS DDR output mode minimizes EMI in sensitive probe cables. Industrial -40 to +85 °C screening supports equipment-room thermal envelopes. Combined with a low-noise front-end LNA, it enables 12-16 channel beamforming arrays.
おすすめ
Cable CMTS Upstream Path
The ADC1412D125HN/C1:5 is well suited to cable modem termination system (CMTS) upstream receivers where multiple DOCSIS channels must be digitized simultaneously. Its 125 MSPS rate captures the full upstream spectrum, while dual channels allow redundant or diversity reception paths. The selectable CMOS or LVDS DDR output gives designers flexibility for legacy ASIC or modern FPGA interfaces. The HVQFN-64 package's exposed pad supports thermal dissipation in densely populated line-card designs.
おすすめ
Radar Signal Acquisition
The ADC1412D125HN/C1:5's 125 MSPS sample rate captures IF radar signals up to ~62.5 MHz (Nyquist), making it suitable for surveillance, weather radar, and automotive radar receiver digitization. The dual channels enable I/Q sampling directly from a quadrature mixer, simplifying analog signal chain design. Its pipelined architecture maintains linearity across full-scale IF inputs, critical for pulse compression. The compact HVQFN-64 footprint allows high-channel-density receivers in phased-array antenna electronics.
おすすめ
High-Speed Test & Measurement Instrumentation
The ADC1412D125HN/C1:5 fits digital oscilloscope, spectrum analyzer, and arbitrary waveform digitizer front-ends. Dual 14-bit channels at 125 MSPS support 2-channel simultaneous sampling, while LVDS DDR outputs deliver high-fidelity data to FPGA-based signal-processing engines. The 72 dBFS SNR preserves measurement accuracy for spectral purity tests. Industrial temperature screening and RoHS compliance simplify integration into laboratory and production test equipment. Pair with high-bandwidth differential input amplifiers for full-bandwidth performance.
おすすめ
Industrial Data Acquisition Systems
The ADC1412D125HN/C1:5 serves high-channel-count industrial DAQ platforms for vibration analysis, sonar, and rotating machinery monitoring. Dual simultaneous 14-bit channels at 125 MSPS support wide dynamic range, while the industrial -40 to +85 °C temperature range tolerates factory-floor environments. The HVQFN-64 footprint with exposed pad enables compact PCB layouts. Engineers often pair this ADC with FPGA-based processing engines for real-time FFT and condition monitoring algorithms.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: ADC1412D125HN/C1:5 — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | ADC1412D125HN/C1 | ADC1412D065HN-C1 | ADC1112D125HN-C18 | ADC1213S125HN-C1 | ADC1410S105HN-C1 |
|---|---|---|---|---|---|---|
| Brand | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors |
| Package | HVQFN-64 (9x9) | HVQFN-64 (9x9) - same | HVQFN-64 (9x9) - same | HVQFN-64 (9x9) - same | HVQFN-64 (9x9) - same | HVQFN-64 (9x9) - same |
| Resolution | 14 bit | 14 bit | 14 bit | 12 bit | 12 bit | 14 bit |
| Channels | 2 (dual) | 2 (dual) | 2 (dual) | 2 (dual) | 1 (single) | 1 (single) |
| Maximum Sample Rate | 125 MSPS | 125 MSPS | 65 MSPS | 125 MSPS | 125 MSPS | 105 MSPS |
| Digital Output Interface | CMOS / LVDS DDR (selectable) | CMOS / LVDS DDR | CMOS / LVDS DDR | CMOS / LVDS DDR | CMOS / LVDS DDR | CMOS / LVDS DDR |
| Operating Temperature | -40 °C to +85 °C | -40 °C to +85 °C | -40 °C to +85 °C | -40 °C to +85 °C | -40 °C to +85 °C | -40 °C to +85 °C |
| Architecture | Pipelined | Pipelined | Pipelined | Pipelined | Pipelined | Pipelined |
| RoHS Compliance | Yes | Yes | Yes | Yes | Yes | Yes |
主な差別化要因
- Dual 14-bit simultaneous sampling at 125 MSPS in single package （vs ADC1213S125HN-C1 (single-channel 12-bit))
- Selectable CMOS or LVDS DDR digital output （vs TI ADS62P48 (LVDS-only))
- Industrial -40 to +85 °C screening standard （vs Consumer-grade SAR ADCs in similar role)
設計ノート
Solder the exposed thermal pad of the HVQFN-64 package to a continuous ground copper pour covering at least 1 cm² for thermal dissipation. Use a 4-layer PCB with dedicated analog and digital ground planes split under the ADC; join them at a single point near the ADC ground pin. Route differential analog inputs (VIN_A+/-, VIN_B+/-) as 100 Ω impedance-matched pairs with length matching within 0.5 mm to preserve 72 dB SNR at 125 MSPS.
Use low-noise LDO regulators (e.g., TPS7A4701RGWR) for the 3.3 V analog supply (VDD_ANA) and a separate LDO for the digital supply (VDD_DIG) to isolate digital switching noise from sensitive analog circuits. Place 10 µF ceramic + 0.1 µF ceramic bypass capacitors as close as possible to each supply pin. The exposed pad must be soldered to a low-impedance ground plane; do not skip this - missing the pad connection can cause 5-10 dB SNR degradation.
Route the LVDS DDR output pairs (D0_A..D13_A, DCLK_A, and channel B equivalents) as 100 Ω differential microstrip lines with length matching within 1 mm across all pairs. Keep LVDS traces away from analog input traces and clock signals to minimize crosstalk. For CMOS output mode, use controlled-impedance single-ended traces (typically 50 Ω) and group the 14 data bits + clock together. Maintain solid ground reference beneath all output traces.
Do not switch between CMOS and LVDS DDR output modes after power-up without re-initializing the device via RESET pin. Per the NXP datasheet, mid-operation mode changes can corrupt sample alignment. Always configure MODE pin before applying clocks. Avoid driving the analog inputs beyond the absolute maximum rating (typically 3.3 V on VDD_ANA); overdrive can permanently damage the input ESD structure. Use a transformer-coupled or fully differential driver (e.g., ADA4937) to maximize SFDR.
Drive the CLK+/CLK- differential clock input with a low-jitter clock source (jitter < 200 fs RMS) to preserve aperture jitter performance at 125 MSPS. Per the NXP datasheet, SNR degrades approximately 2 dB per 100 fs of additional clock jitter above the part's intrinsic aperture jitter. Use a clock buffer or transformer (e.g., ADT1-1WT) to convert single-ended oscillator outputs to differential while maintaining low jitter.
コンプライアンス情報
RoHS and lead-free compliance confirmed per NXP product page. Industrial screening level (-40 to +85 °C). Not AEC-Q100 qualified - this is a commercial/industrial ADC. Halogen-free status not explicitly stated in verified data.
