ADS5296RGCR - 12-Bit 80MSPS 8-Channel ADC | Texas Instruments
部品番号: ADS5296RGCR ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $67.5 | $67.50 |
| 10 | $60.75 | $607.50 |
| 100 | $54 | $5,400.00 |
| 500 | $47.25 | $23,625.00 |
| 1,000 | $43.2 | $43,200.00 |
| 3,000 | $38.8 | $116,400.00 |
ADS5296RGCR 概要
An analog-to-digital converter (ADC) is a mixed-signal integrated circuit that converts real-world analog voltages into discrete digital codes for processors, FPGAs, or DSPs to analyze. Within the converter hierarchy, the ADS5296 belongs to the pipeline ADC subclass, which uses a multi-stage switched-capacitor architecture to achieve high sampling rates (tens to hundreds of MSPS) at moderate resolution (8-14 bits); pipelined ADCs sit between successive-approximation (SAR) ADCs (slow, high-resolution) and flash ADCs (fast, low-resolution). Pipelined ADCs are the workhorse of medical imaging, communications, and multi-channel data acquisition.
Key features include 12-bit resolution, 80 MSPS maximum sampling rate, 8 simultaneous sampling channels, LVDS/CMOS digital outputs, SNR of 70 dBFS at 10 MHz input, SFDR of 86 dBc, and 1.8 V analog supply with 3.3 V digital I/O supply. The integrated digital gain from 0 dB to 12 dB and per-channel offset correction up to +/- 96 LSB reduce system calibration complexity.
Architecturally, the ADS5296 uses a fully differential switched-capacitor pipeline core with a proprietary multi-bit per-stage architecture and on-chip dithering to enhance spurious-free dynamic range. The eight ADC channels operate from a shared PLL-derived internal clock and a shared bandgap reference, ensuring tight inter-channel gain and offset matching for beamforming and parallel sampling applications.
Typical applications include medical imaging ultrasound receivers, multi-channel communications test equipment, portable instrumentation, security and surveillance imaging, and phased-array radar preprocessing. The 80 MSPS per-channel rate supports IF sampling in communications and direct-downconversion of baseband signals up to approximately 35 MHz.
Design considerations for the ADS5296RGCR include careful PCB layout to maintain the LVDS output timing budget; a low-jitter external clock is essential because aperture-jitter sensitivity sets the SNR ceiling at high input frequencies. The VQFN-64 exposed pad must be soldered to a continuous ground plane for both thermal dissipation (the RGC package carries a low thermal resistance) and low-impedance return paths for the analog inputs.
This page synthesizes distributor pricing as of 2026-10-11, drop-in RGC-64 alternatives, and PCB layout guidance that go beyond the manufacturer datasheet alone.
ドロップイン代替品: ADS5296RGCR — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: ADS5296RGCR （同一形状・フットプリント） — 相違点: Digital I/O Supply, Operating Temperature Range, Package.
クイック比較ツール — 並列比較する代替部品を選択:
ADS5296ARGCT
✅ ドロップイン📋 参考代替品（カタログ未掲載）
ADS5296RGCT
✅ ドロップイン✓ 在庫あり
$43.5 / 個
データシートを見る →ADS5295RGCR
✅ ドロップイン📋 参考代替品（カタログ未掲載）
ADS5294RGCR
✅ ドロップイン📋 参考代替品（カタログ未掲載）
ADS5292RGCR
✅ ドロップイン📋 参考代替品（カタログ未掲載）
ADS5296RGCR 最大定格＆電気的特性
| 分解能 | 12 bits |
| Number of Channels | 8 |
| Sampling Rate (Max) | 80 MSPS per channel |
| Architecture | Pipelined |
| Input Type | Differential |
| Analog Supply Voltage | 1.8 V |
| Digital I/O Supply | 3.3 V (LVDS outputs) |
| SNR | 70 dBFS at fIN = 10 MHz |
| SFDR | 86 dBc |
| Digital Output Format | LVDS / CMOS selectable |
| パッケージ | VQFN-64 (RGC) 9 mm x 9 mm |
| 実装タイプ | Surface Mount |
| 動作温度範囲 | -40 C to +85 C |
| Lead Free / RoHS | Yes / Compliant |
| On-Chip Features | Digital gain 0-12 dB, per-channel offset correction, internal dither |
ADS5296RGCR ピン構成
| ピン 1 | AVDD1P8 — Analog 1.8 V supply (channel 1 ADC) |
| ピン 2 | AVSS1 — Analog ground (channel 1 ADC) |
| ピン 3 | AIN1P — Channel 1 differential analog input positive |
| ピン 4 | AIN1N — Channel 1 differential analog input negative |
| ピン 5 | AVSS1 — Analog ground (channel 1 ADC) |
| ピン 6 | AVDD1P8 — Analog 1.8 V supply (channel 2 ADC) |
| ピン 7 | AVSS2 — Analog ground (channel 2 ADC) |
| ピン 8 | AIN2P — Channel 2 differential analog input positive |
| ピン 9 | AIN2N — Channel 2 differential analog input negative |
| ピン 10 | AVSS2 — Analog ground (channel 2 ADC) |
| ピン 11 | AVDD1P8 — Analog 1.8 V supply (channel 3 ADC) |
| ピン 12 | AVSS3 — Analog ground (channel 3 ADC) |
| ピン 13 | AIN3P — Channel 3 differential analog input positive |
| ピン 14 | AIN3N — Channel 3 differential analog input negative |
| ピン 15 | AVSS3 — Analog ground (channel 3 ADC) |
| ピン 16 | AVDD1P8 — Analog 1.8 V supply (channel 4 ADC) |
| ピン 17 | AVSS4 — Analog ground (channel 4 ADC) |
| ピン 18 | AIN4P — Channel 4 differential analog input positive |
| ピン 19 | AIN4N — Channel 4 differential analog input negative |
| ピン 20 | AVSS4 — Analog ground (channel 4 ADC) |
| ピン 21 | AVDD1P8 — Analog 1.8 V supply (channels 5-8) |
| ピン 22 | AVSS5 — Analog ground (channel 5 ADC) |
| ピン 23 | AIN5P — Channel 5 differential analog input positive |
| ピン 24 | AIN5N — Channel 5 differential analog input negative |
| ピン 25 | AVSS5 — Analog ground (channel 5 ADC) |
| ピン 26 | AVDD1P8 — Analog 1.8 V supply (channel 6 ADC) |
| ピン 27 | AVSS6 — Analog ground (channel 6 ADC) |
| ピン 28 | AIN6P — Channel 6 differential analog input positive |
| ピン 29 | AIN6N — Channel 6 differential analog input negative |
| ピン 30 | AVSS6 — Analog ground (channel 6 ADC) |
| ピン 31 | AVDD1P8 — Analog 1.8 V supply (channel 7 ADC) |
| ピン 32 | AVSS7 — Analog ground (channel 7 ADC) |
| ピン 33 | AIN7P — Channel 7 differential analog input positive |
| ピン 34 | AIN7N — Channel 7 differential analog input negative |
| ピン 35 | AVSS7 — Analog ground (channel 7 ADC) |
| ピン 36 | AVDD1P8 — Analog 1.8 V supply (channel 8 ADC) |
| ピン 37 | AVSS8 — Analog ground (channel 8 ADC) |
| ピン 38 | AIN8P — Channel 8 differential analog input positive |
| ピン 39 | AIN8N — Channel 8 differential analog input negative |
| ピン 40 | AVSS8 — Analog ground (channel 8 ADC) |
| ピン 41 | VCM — Common-mode voltage output (bias for analog input stage) |
| ピン 42 | REFP — Internal reference positive (decouple to REFN) |
| ピン 43 | REFN — Internal reference negative (decouple to REFP) |
| ピン 44 | AVDD1P8 — Analog 1.8 V supply (reference / clock tree) |
| ピン 45 | AVSS — Analog ground (reference / clock tree) |
| ピン 46 | CLKP — Differential sample clock positive |
| ピン 47 | CLKN — Differential sample clock negative |
| ピン 48 | AVSS — Analog ground (clock tree) |
| ピン 49 | RESET — Active-low hardware reset |
| ピン 50 | PDN — Active-low power-down (per-channel selectable via register) |
| ピン 51 | SCLK — Serial interface clock |
| ピン 52 | SDATA — Serial interface data |
| ピン 53 | SEN — Serial interface enable (active low) |
| ピン 54 | AVDD1P8 — Analog 1.8 V supply (digital core) |
| ピン 55 | DGND — Digital ground (digital core) |
| ピン 56 | DRVDD — Digital output driver supply (3.3 V LVDS / 1.8 V CMOS) |
| ピン 57 | DRGND — Digital output driver ground |
| ピン 58 | DCLK_P — LVDS output bit clock positive (DDR) |
| ピン 59 | DCLK_N — LVDS output bit clock negative |
| ピン 60 | FRCLK_P — LVDS output frame clock positive |
| ピン 61 | FRCLK_N — LVDS output frame clock negative |
| ピン 62 | DOUT_P — LVDS data output positive |
| ピン 63 | DOUT_N — LVDS data output negative |
| ピン 64 | NC — Not connected (per datasheet) |
主な用途
ADS5296RGCR の用途: 6 件s: Medical Ultrasound Imaging Receiver, Phased-Array Radar Preprocessing, Multi-Channel Communications Test Equipment, Industrial Multi-Channel Data Acquisition, Surveillance and Security Imaging, Portable Instrumentation and Handheld Oscilloscopes.
Medical Ultrasound Imaging Receiver
The ADS5296RGCR is purpose-built for medical ultrasound front-end digitisation. Its 8 simultaneously-sampling channels at 80 MSPS per channel digitise the outputs of a 1:8 phased-array transducer, while the on-chip digital gain (0 to 12 dB) replaces external TGC stages and reduces BOM. Per-channel offset correction up to +/- 96 LSB lowers the system calibration burden for high-channel-count carts, and 70 dBFS SNR preserves the dynamic range required for harmonic and contrast imaging. The exposed-pad VQFN-64 (RGC) package keeps the receive chain compact, allowing dense probe-head electronics with low thermal rise.
おすすめ
Phased-Array Radar Preprocessing
Eight matched ADC channels make the ADS5296RGCR well suited to digital-array radar where beamforming requires tight inter-channel amplitude and phase matching. The shared internal clock tree and shared reference keep channel-to-channel gain variation within the calibration budget, while 80 MSPS per channel supports direct IF sampling of L-band radar returns at up to about 30 MHz carrier. The 86 dBc SFDR prevents adjacent-target masks from being masked by ADC spurs. The RGC-64 9x9 mm footprint plus integrated digital processing reduces PCB area compared with eight discrete ADC channels.
おすすめ
Multi-Channel Communications Test Equipment
The ADS5296RGCR's 70 dBFS SNR and -86 dBc SFDR enable wide-bandwidth digitisation of IF and baseband signals in wireless test instruments, spectrum analysers, and signal-intelligence recorders. With 8 channels at 80 MSPS, designers can capture multiple antennas or carriers simultaneously, eliminating the timing skew that would otherwise arise from sequential sampling. LVDS outputs maintain timing integrity over backplane traces to the FPGA processor. The 1.8 V analog supply keeps portable-instrument power budgets manageable.
おすすめ
Industrial Multi-Channel Data Acquisition
Eight channels at 12-bit resolution are well matched to industrial data-acquisition modules such as vibration analysers, sonar hydrophones, and multi-loop process control. Each channel can be AC- or DC-coupled with its own front-end, then synchronised via the ADS5296RGCR's shared clock for coherent multi-axis sampling. The RGC-64 package and integrated digital calibration reduce board space compared with eight discrete ADCs. Per-channel gain is software-programmable, so the same hardware can digitise low-level vibration and high-amplitude shock waveforms with no external attenuator switching.
おすすめ
Surveillance and Security Imaging
The ADS5296RGCR provides the simultaneous 8-channel digitisation needed by multi-camera security and surveillance platforms that perform real-time image processing on FPGA. The 80 MSPS per-channel rate supports oversampled video bandwidth, while integrated digital gain simplifies low-light scenarios by replacing per-channel analog AGC. The compact VQFN-64 (RGC) package and shared reference simplify thermal management in space-constrained camera hubs. FPGA LVDS capture directly into the digital-processing pipeline eliminates an intermediate resampling stage.
おすすめ
Portable Instrumentation and Handheld Oscilloscopes
Battery-powered oscilloscopes and portable analysers benefit from the ADS5296RGCR's 1.8 V analog supply and 8 channels in a single 9x9 mm footprint, halving PCB area versus discrete multi-ADC designs. The integrated digital offset and gain correction reduce factory calibration time per channel, which directly lowers test cost in handheld instruments. The 80 MSPS per-channel bandwidth captures fast transients and serial-bus signals, while the LVDS interface preserves signal integrity to the processor even at peak sampling rates. Engineers reuse the same ADS5296 footprint across 2-channel and 8-channel platforms for economies of scale.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: ADS5296RGCR — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | ADS5296ARGCT | ADS5296RGCT | ADS5295RGCR | ADS5294RGCR | ADS5292RGCR |
|---|---|---|---|---|---|---|
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Package | VQFN-64 (RGC) 9x9 mm | VQFN-64 (RGC) 9x9 mm - same | VQFN-64 (RGC) 9x9 mm - same | VQFN-64 (RGC) 9x9 mm - same | VQFN-64 (RGC) 9x9 mm - same | VQFN-64 (RGC) 9x9 mm - same |
| Resolution | 12 bits | 12 bits | 12 bits | 10 bits | 10 bits | 12 bits |
| Sampling Rate (Max) | 80 MSPS/ch | 80 MSPS/ch | 80 MSPS/ch | 80 MSPS/ch | 50 MSPS/ch | 80 MSPS/ch (10-bit effective after decimation) |
| Channel Count | 8 | 8 | 8 | 8 | 8 | 8 |
| Analog Supply | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V |
| Digital Output | LVDS / CMOS | LVDS / CMOS | LVDS / CMOS | LVDS / CMOS | LVDS / CMOS | LVDS / CMOS |
| Silicon Revision / Reel Code | ADS5296 die, large reel (-R) | ADS5296A silicon revision, small reel (-T) | ADS5296 die, small reel (-T) | 10-bit ADS5295 die | 10-bit ADS5294 die (slower) | 12-bit decimated ADS5292 die |
主な差別化要因
- Highest SNR among same-package 8-channel ADS529x family members at 80 MSPS （vs ADS5295RGCR)
- Sampling rate twice that of ADS5294 （vs ADS5294RGCR)
- Full-rate sampling rather than decimated 12-bit output （vs ADS5292RGCR)
- Identical silicon die to ADS5296ARGCT （vs ADS5296ARGCT)
設計ノート
Estimated: The VQFN-64 (RGC) 9x9 mm exposed pad must be soldered to a continuous, low-impedance analog ground plane through an array of 0.3 mm thermal vias on a 1.0 mm pitch. Differential analog input traces should be length-matched within 0.13 mm (5 mil) per channel and routed over a contiguous ground plane on the layer directly beneath; this keeps capacitive imbalance below the LVDS skew budget and preserves the 70 dBFS SNR figure at 10 MHz input.
Choose a clock source with sub-200 fs RMS jitter when running the ADS5296RGCR at 80 MSPS, otherwise aperture-jitter degradation will erode SNR at high input frequencies. Estimated: each 1 ps of clock jitter erodes SNR by approximately 0.6 dB at fIN = 30 MHz, and the datasheet aperture-jitter spec is reached only with low-noise LVDS or LVPECL clock fan-out rather than CMOS oscillators.
AVDD1P8 (1.8 V analog), DRVDD (3.3 V driver), and the internal reference REFP/REFN each require a separate 1 uF + 0.1 uF ceramic decoupling pair placed within 5 mm of the supply pins, plus a ferrite bead to isolate the analog supply from upstream switching noise. Estimated: at 80 MSPS the analog supply is the dominant power draw; an LDO with 30 dB PSRR at 1 MHz is recommended for the analog rail.
When using the LVDS output mode, route the DCLK_P/N, FRCLK_P/N, and DOUT_P/N pairs as 100 ohm differential lines, length-matched within 0.5 mm, with no splits in the reference plane beneath them. If the FPGA receiver-side requires AC-coupling capacitors, place them within 5 mm of the FPGA, not the ADC, to keep the LVDS common-mode voltage within TI's recommended range.
コンプライアンス情報
RoHS-compliant VQFN-64 (RGC) industrial-grade ADC from Texas Instruments. Not AEC-Q100 qualified - the family is intended for medical, industrial, and communications applications rather than automotive.
