ADS5517IRGZ25 - 11-Bit 200MSPS ADC, DDR LVDS/CMOS | Texas Instruments
部品番号: ADS5517IRGZ25 ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $24.5 | $24.50 |
| 10 | $22.05 | $220.50 |
| 100 | $19.6 | $1,960.00 |
| 500 | $17.5 | $8,750.00 |
| 1,000 | $15.4 | $15,400.00 |
ADS5517IRGZ25 概要
A pipelined ADC is a high-speed successive-sampling architecture that uses cascaded low-resolution flash stages with residue amplification to digitize analog inputs at hundreds of megasamples per second. Pipelined ADCs are widely used as the converter workhorse for high-speed data acquisition, software-defined radio, digital oscilloscopes and communications infrastructure, where they sit between the analog front end (amplifier, anti-alias filter) and the digital signal processor / FPGA.
Key features include low power consumption in CMOS mode, programmable analog input bandwidth, an internal reference with external-reference option, a high-bandwidth input clock buffer with low jitter, and DDR LVDS / DDR CMOS digital output modes. Its pipelined core with digital error correction maintains spurious-free dynamic range (SFDR) and signal-to-noise ratio (SNR) performance at full-scale inputs.
Typical applications include wireless base-station IF sampling, test-and-measurement instrumentation, medical imaging digitizers, defense radar receivers, and high-speed industrial digitizers. The 200-MSPS sampling rate supports multicarrier GSM / LTE / W-CDMA receivers and gives substantial decimation headroom for narrowband DSP.
When designing with this device, allocate separate analog and digital ground planes with a single-point tie beneath the exposed pad, and place the 3.3V AVDD / 1.8V DRVDD decoupling capacitors as close to the package as possible. Confirm that the downstream receiver supports the chosen LVDS-data-rate and DDR-CMOS timing budget before finalizing the schematic.
ドロップイン代替品: ADS5517IRGZ25 — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
クイック比較ツール — 並列比較する代替部品を選択:
ADS5517IRGZR
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ADS5517IRGZT
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ADS5517IRGZRG4
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ADS5517IRGZTG4
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ADS6125IRGZ
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ADS6145IRGZ
✅ ドロップイン📋 参考代替品（カタログ未掲載）
ADS5517IRGZ25 最大定格＆電気的特性
| 分解能 | 11 bit |
| Sample Rate | 200 MSPS |
| Number of Inputs | 1 |
| Architecture | Pipelined |
| Input Type | Differential |
| Analog Supply Voltage | 3.3 V |
| Digital Supply Voltage | 1.8 V |
| Digital Output Interface | DDR LVDS / DDR CMOS (serial or parallel) |
| Reference | Internal with external-reference option |
| Analog Input Bandwidth | Wideband (programmable input full-scale) |
| 動作温度範囲 | -40 C to +85 C (industrial) |
| パッケージ | 48-pin VQFN (RGZ, 7x7 mm) |
| 実装タイプ | Surface Mount |
| MSLレベル | 3 (168 hours) |
| RoHS ステータス | Compliant |
ADS5517IRGZ25 ピン構成
| ピン 1 | AVDD — Analog 3.3V supply |
| ピン 2 | AVDD — Analog 3.3V supply |
| ピン 3 | AGND — Analog ground |
| ピン 4 | INP — Differential analog input (positive) |
| ピン 5 | INM — Differential analog input (negative) |
| ピン 6 | AGND — Analog ground |
| ピン 7 | AGND — Analog ground |
| ピン 8 | REFBA — Reference bypass A |
| ピン 9 | REFTB — Reference bypass B |
| ピン 10 | REF — Reference I/O |
| ピン 11 | REFM — Reference minus / ground |
| ピン 12 | AGND — Analog ground |
| ピン 13 | AVDD — Analog 3.3V supply |
| ピン 14 | AVDD — Analog 3.3V supply |
| ピン 15 | CLKP — Differential clock input (positive) |
| ピン 16 | CLKM — Differential clock input (negative) |
| ピン 17 | AGND — Analog ground |
| ピン 18 | AGND — Analog ground |
| ピン 19 | DRVDD — Digital 1.8V supply |
| ピン 20 | DRVDD — Digital 1.8V supply |
| ピン 21 | DRGND — Digital ground |
| ピン 22 | DFS — Data format select |
| ピン 23 | OE — Output enable (active low) |
| ピン 24 | RESET — Hardware reset (active low) |
| ピン 25 | DRGND — Digital ground |
| ピン 26 | DCLKP — DDR LVDS clock output (positive) |
| ピン 27 | DCLKM — DDR LVDS clock output (negative) |
| ピン 28 | DRGND — Digital ground |
| ピン 29 | D0P — LVDS data output 0 positive |
| ピン 30 | D0M — LVDS data output 0 negative |
| ピン 31 | D1P — LVDS data output 1 positive |
| ピン 32 | D1M — LVDS data output 1 negative |
| ピン 33 | DRGND — Digital ground |
| ピン 34 | D2P — LVDS data output 2 positive |
| ピン 35 | D2M — LVDS data output 2 negative |
| ピン 36 | D3P — LVDS data output 3 positive |
| ピン 37 | D3M — LVDS data output 3 negative |
| ピン 38 | D4P — LVDS data output 4 positive |
| ピン 39 | D4M — LVDS data output 4 negative |
| ピン 40 | DRGND — Digital ground |
| ピン 41 | D5P — LVDS data output 5 positive |
| ピン 42 | D5M — LVDS data output 5 negative |
| ピン 43 | D6P — LVDS data output 6 positive |
| ピン 44 | D6M — LVDS data output 6 negative |
| ピン 45 | D7P — LVDS data output 7 positive |
| ピン 46 | D7M — LVDS data output 7 negative |
| ピン 47 | DRVDD — Digital 1.8V supply |
| ピン 48 | DRGND — Digital ground |
主な用途
ADS5517IRGZ25 の用途: 6 件s: Wireless Base-Station IF Sampling, Test and Measurement Instrumentation, Medical Imaging Digitizer, Defense Radar and SIGINT Receivers, High-Speed Industrial Digitizers, Software Defined Radio Front End.
Wireless Base-Station IF Sampling
The ADS5517IRGZ25's 200 MSPS sampling rate and 11-bit resolution make it ideal for intermediate-frequency sampling in 2G/3G/LTE base-station receivers. The pipelined core digitizes IF outputs of the analog front end, and the DDR LVDS / DDR CMOS outputs feed directly into an FPGA digital down-converter without interface glue logic. With 3.3V AVDD and 1.8V DRVDD operation, the ADC integrates cleanly behind TI's TRF3711 or similar downconverters used in macro-cell basestation designs.
おすすめ
Test and Measurement Instrumentation
In digitizer cards, oscilloscope front-ends and spectrum-analyzer IF strips, the ADS5517IRGZ25 captures wideband analog signals at 200 MSPS, preserving transient fidelity. Its programmable analog input full-scale (2 Vpp or 1 Vpp) lets designers trade dynamic range for SNR based on the source amplitude. Industrial temperature-grade operation (-40C to +85C) supports production-floor test racks without additional thermal conditioning.
おすすめ
Medical Imaging Digitizer
The 11-bit resolution and 200 MSPS throughput of the ADS5517IRGZ25 suit ultrasound beamformer signal chains and other medical imaging front ends where the ADC must capture high-frequency transducer echoes. Differential analog inputs reject common-mode pickup from the imaging probe, while the DDR LVDS interface transfers digitized RF to the array processor at low EMI. Single 3.3V / 1.8V supply operation simplifies the medical-grade isolation barrier design.
おすすめ
Defense Radar and SIGINT Receivers
The pipelined architecture of the ADS5517IRGZ25 supports the wide instantaneous bandwidth required for electronic-warfare and radar IF stages. Programmable input bandwidth and high SFDR at high input frequencies translate directly into improved target-discrimination performance. The 48-pin VQFN footprint integrates into SWaP-constrained platforms alongside Xilinx Kintex/XCZU-class FPGAs for real-time pulse processing.
おすすめ
High-Speed Industrial Digitizers
Industrial flaw-detection, vibration-analysis and motor-control digitizers leverage the ADS5517IRGZ25's 200 MSPS capture rate to record transient waveforms without aliasing. The 48-pin VQFN package provides a compact, surface-mountable form factor for dense multi-channel boards. With industrial temperature-grade operation, the ADC ships directly into factory-floor data-acquisition modules operating from -40C to +85C.
おすすめ
Software Defined Radio Front End
SDR platforms benefit from the ADS5517IRGZ25's combination of 200 MSPS, 11-bit resolution and selectable LVDS/CMOS interfaces for direct FPGA connectivity. Sampling at-or-above 200 MSPS provides sufficient decimation headroom for digital down-conversion of narrowband waveforms while avoiding folding. Industrial temperature grade supports outdoor and vehicular SDR installations, including public-safety and amateur-radio transceivers.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: ADS5517IRGZ25 — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | ADS5517IRGZR | ADS5517IRGZT | ADS5517IRGZRG4 | ADS6125IRGZ | ADS6145IRGZ |
|---|---|---|---|---|---|---|
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Package | VQFN-48 (RGZ, 7x7 mm) | VQFN-48 (RGZ, 7x7 mm) - same | VQFN-48 (RGZ, 7x7 mm) - same | VQFN-48 (RGZ, 7x7 mm) - same | VQFN-48 (RGZ, 7x7 mm) - same | VQFN-48 (RGZ, 7x7 mm) - same |
| Resolution | 11 bit | 11 bit | 11 bit | 11 bit | 12 bit | 14 bit |
| Sample Rate | 200 MSPS | 200 MSPS | 200 MSPS | 200 MSPS | 200 MSPS | 200 MSPS |
| Analog Supply | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V | |
| Digital Supply | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V | |
| Output Interface | DDR LVDS / DDR CMOS | DDR LVDS / DDR CMOS | DDR LVDS / DDR CMOS | DDR LVDS / DDR CMOS | DDR LVDS / DDR CMOS | |
| Operating Temperature | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C |
主な差別化要因
- Lowest-bits variant of the ADS5x17 family in shared pinout （vs ADS6125IRGZ)
- Drop-in upgrade path to higher resolution （vs ADS6145IRGZ)
- DDR LVDS / DDR CMOS dual interface （vs ADS5517 family CMOS-only cousins)
設計ノート
Use a single solid ground plane partitioned into AGND and DRGND regions tied together under the exposed pad of the RGZ-48 package. Place 0.1 uF X7R ceramic decoupling capacitors as close as possible to every AVDD/DRVDD pin and add a 10 uF bulk capacitor near the analog supply input. Maintain matched 50 ohm single-ended (or 100 ohm differential) routing for the analog input and clock traces to preserve SFDR.
Estimated: with 3.3V AVDD drawing roughly 350 mW and 1.8V DRVDD drawing roughly 130 mW, total power dissipation sits near 480 mW. The RGZ-48 VQFN's exposed pad must be soldered to a continuous copper pour of at least 1 sq inch to keep junction temperature within the -40C to +85C industrial range; without this, junction temperature rise can exceed 25 C/W theta_JA.
Do not float the RESET pin - drive it from the FPGA or a pull-up tied to DRVDD to avoid unintended reset events. Avoid driving the analog input directly from a high-impedance source; buffer with a low-noise, low-distortion driver such as the OPA1612 or THS3201. Confirm that the receiver's DDR LVDS skew tolerance matches the ADC's data-valid window before finalizing capture timing.
The DDR LVDS data outputs toggle at the sample rate and should be length-matched within 2 mm of the DCLKP/DCLKM pair to minimize ISI. Use a 100 ohm differential transmission-line geometry with controlled impedance; do not allow stubs on the data lines. Treat the analog inputs as the most sensitive nets - keep them short and symmetric.
コンプライアンス情報
Industrial temperature grade (-40 C to +85 C). Pb-free / RoHS per TI product page; G4 suffix variants explicitly call out RoHS compliance in the part number.
