ADS6124IRHB25 - 12-Bit 105MSPS Low-Power ADC | Texas Instruments
部品番号: ADS6124IRHB25 ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $36.5 | $36.50 |
| 10 | $32.4 | $324.00 |
| 100 | $27.85 | $2,785.00 |
| 500 | $24.2 | $12,100.00 |
| 1,000 | $21.5 | $21,500.00 |
ADS6124IRHB25 概要
An ADC (analog-to-digital converter) is a semiconductor device that converts continuous analog signals into discrete digital codes, serving as the bridge between real-world analog phenomena (sensor outputs, RF signals, audio) and digital signal processing. Within the broader taxonomy, the ADS6124 is a successive-approximation/pipelined ADC, the dominant architecture for medium-to-high-speed data acquisition. Pipelined ADCs use a multi-stage architecture with sub-ADCs and DACs to achieve high sample rates at moderate resolution, balancing speed and accuracy through a tradeoff between latency and resolution.
Key features of the ADS6124IRHB25 include 12-bit resolution, 105 MSPS maximum sampling rate, LVDS/CMOS selectable digital interface, low power architecture, internal reference, and an industrial temperature range of -40C to +85C. The part comes in a compact 32-VQFN exposed-pad package that provides improved thermal performance for the sustained operation required at full sample rate.
Typical applications include communications base-station receivers, test and measurement equipment, medical imaging front-ends, multi-channel data acquisition systems, and radar signal processing. The wide input bandwidth and LVDS output option make it well-suited for IF sampling and high-density channel card designs.
When designing with this ADC, pay close attention to the analog input network: a transformer or differential driver is normally used to drive the analog inputs to maximize SFDR. Decoupling the AVDD and DRVDD rails with low-ESR ceramic capacitors placed close to the package improves noise immunity, and the exposed pad must be soldered to a sufficiently large PCB ground pour for thermal dissipation.
ドロップイン代替品: ADS6124IRHB25 — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: ADS6124IRHB25 （同一形状・フットプリント） — 相違点: Package, RoHS Status, Analog Supply Voltage, Output Interface, Digital Supply Voltage.
クイック比較ツール — 並列比較する代替部品を選択:
ADS6125IRHBR
✅ ドロップイン📋 参考代替品（カタログ未掲載）
ADS6123IRHBR
✅ ドロップイン✓ 在庫あり
$9.4 / 個
データシートを見る →ADS6122IRHBR
✅ ドロップイン✓ 在庫あり
$12.5 / 個
データシートを見る →ADS6124IRHBR
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
ADS6124IRHB25 最大定格＆電気的特性
| 分解能 | 12 bits |
| Number of Inputs | 1 |
| サンプリングレート | 105 MSPS |
| Converter Architecture | Pipelined |
| Output Interface | DDR LVDS or Parallel CMOS (selectable) |
| Digital Supply Voltage (DRVDD) | 1.8 V to 3.3 V |
| Analog Supply Voltage (AVDD) | 3.3 V (typical) |
| Input Type | Differential |
| Reference Type | Internal (external reference mode supported) |
| 動作温度 | -40C to +85C |
| パッケージ | 32-VQFN (5x5 mm) with exposed pad |
| 実装タイプ | Surface Mount |
| RoHS ステータス | Compliant |
ADS6124IRHB25 ピン構成
| ピン 1 | AVDD — Analog supply (3.3 V typical) |
| ピン 2 | GND — Analog ground |
| ピン 3 | INP — Differential analog input positive |
| ピン 4 | INN — Differential analog input negative |
| ピン 5 | VCM — Common-mode voltage output |
| ピン 6 | REFT — Reference decoupling top |
| ピン 7 | REFB — Reference decoupling bottom |
| ピン 8 | GND — Ground |
| ピン 9 | RESET — Reset / power-down control |
| ピン 10 | SCLK — Serial interface clock |
| ピン 11 | SEN — Serial interface enable |
| ピン 12 | SDATA — Serial interface data |
| ピン 13 | CLK — Sample clock input |
| ピン 14 | CLKB — Complementary sample clock input |
| ピン 15 | GND — Ground |
| ピン 16 | DRVDD — Digital output supply |
| ピン 17 | DRVSS — Digital output ground |
| ピン 18 | D0 — Data output bit D0 |
| ピン 19 | D1 — Data output bit D1 |
| ピン 20 | D2 — Data output bit D2 |
| ピン 21 | D3 — Data output bit D3 |
| ピン 22 | D4 — Data output bit D4 |
| ピン 23 | D5 — Data output bit D5 |
| ピン 24 | D6 — Data output bit D6 |
| ピン 25 | D7 — Data output bit D7 |
| ピン 26 | D8 — Data output bit D8 |
| ピン 27 | D9 — Data output bit D9 |
| ピン 28 | D10 — Data output bit D10 |
| ピン 29 | D11 — Data output bit D11 |
| ピン 30 | MODE — Output mode / format select |
| ピン 31 | OE — Output enable (active high) |
| ピン 32 | AGND/EP — Exposed thermal pad - ground |
主な用途
ADS6124IRHB25 の用途: 6 件s: Communications Base-Station Receiver IF Sampling, Test and Measurement Instrumentation Digitizer, Medical Ultrasound Imaging Front-End, Radar and Lidar Signal Processing, Industrial Multi-Channel Data Acquisition, Software-Defined Radio (SDR) Wideband Front-End.
Communications Base-Station Receiver IF Sampling
The ADS6124IRHB25 is well suited to communications base-station receivers that perform direct IF sampling of intermediate-frequency signals up to about 50 MHz. With 12-bit resolution and 105 MSPS sampling, the converter preserves ample dynamic range for demodulation while DDR LVDS output pairs minimize routing congestion between ADC and FPGA. Designers place a balun or differential driver at the analog input to maximize SFDR, which is critical for adjacent-channel rejection. Compared to a dual-channel converter the single-channel 32-VQFN footprint enables dense multi-channel receiver cards where PCB real-estate is at a premium.
おすすめ
Test and Measurement Instrumentation Digitizer
Test-and-measurement digitizers benefit from the ADS6124IRHB25 combination of 12 bits, 105 MSPS, and the ability to select CMOS or DDR LVDS outputs at power-up. An FPGA downstream captures either CMOS-wide parallel buses or the more compact DDR LVDS pairs to fit a multi-channel digitizer on a single board. The exposed thermal pad of the 32-VQFN aids sustained operation at full sample rate without exceeding the 85C industrial junction limit. Designers size external anti-alias filters against the 105 MHz Nyquist, and decoupling on AVDD / DRVDD with low-ESR 100 nF and 10 uF ceramics is essential for preserving SNR.
おすすめ
Medical Ultrasound Imaging Front-End
In medical ultrasound beamformers, the ADS6124IRHB25 is used as the per-channel digitizer after the TGC/LNA stage, where its 12-bit resolution and 105 MSPS sampling rate are sufficient for capturing returning echoes at IF frequencies up to 40 MHz. The DDR LVDS output minimizes the FPGA pin count per channel, which is critical in dense 64- and 128-channel beamformer boards. The internal voltage reference reduces per-channel board area and simplifies calibration across arrays. Power dissipation at 105 MSPS is well within the thermal envelope of the 32-VQFN package when the exposed pad is properly soldered to a continuous ground pour.
おすすめ
Radar and Lidar Signal Processing
Radar pulse receivers and lidar detection front-ends can leverage the ADS6124IRHB25 to digitize intermediate-frequency echo signals at 105 MSPS with 12 bits of resolution. The pipelined core provides constant aperture delay which preserves phase alignment across channels - critical for coherent beamforming in phased-array radar. The DDR LVDS interface allows the data stream to be captured cleanly into an FPGA even at the maximum sample rate, and the single-channel 32-VQFN footprint supports dense multi-element antenna arrays. For applications below 80 MSPS, designers often use the ADS6123IRHBR as a more cost-effective drop-in alternative.
おすすめ
Industrial Multi-Channel Data Acquisition
Industrial data-acquisition systems (DAQ) often use multiple ADS6124IRHB25 parts in parallel to increase channel density because the single-channel 32-VQFN (5x5 mm) footprint preserves board area for downstream signal conditioning. The 105 MSPS sample rate enables high-bandwidth vibration, ultrasonic, or strain-gauge capture, and the selectable DDR LVDS / CMOS output lets the designer interface to either an FPGA or a high-performance MCU. Industrial temperature grade (-40C to +85C) supports factory-floor deployment. Proper PCB layout - including a continuous ground pour on the exposed pad and locally decoupled analog/digital supplies - is mandatory to keep SNR within spec.
おすすめ
Software-Defined Radio (SDR) Wideband Front-End
Software-defined radio (SDR) wideband front-ends require wide RF input bandwidth and fast sample rates to capture multiple simultaneous bands. The ADS6124IRHB25's pipelined ADC architecture and 105 MSPS sample rate support HF/VHF digitizer cards used in SDR platforms. An analog anti-alias filter precedes the converter and limits out-of-band noise to within the 12-bit quantizer noise floor, after which the digital stream is captured by an FPGA in DDR LVDS mode for real-time DSP. For SDR platforms targeting higher instantaneous bandwidth (up to ~62 MHz Nyquist), upgrading to the ADS6125IRHBR (125 MSPS, same package) is a board-level drop-in upgrade.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: ADS6124IRHB25 — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | ADS6125IRHBR | ADS6123IRHBR | ADS6122IRHBR | ADS6124IRHBR |
|---|---|---|---|---|---|
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Package | 32-VQFN (5x5) | 32-VQFN (5x5) - same | 32-VQFN (5x5) - same | 32-VQFN (5x5) - same | 32-VQFN (5x5) - same |
| Resolution | 12 bits | 12 bits | 12 bits | 12 bits | 12 bits |
| Max Sampling Rate | 105 MSPS | 125 MSPS (+19%) | 80 MSPS (-24%) | 65 MSPS (-38%) | 105 MSPS (same) |
| Number of Inputs | 1 | 1 | 1 | 1 | 1 |
| Architecture | Pipelined | Pipelined | Pipelined | Pipelined | Pipelined |
| Output Interface | DDR LVDS / Parallel CMOS | DDR LVDS / Parallel CMOS | DDR LVDS / Parallel CMOS | DDR LVDS / Parallel CMOS | DDR LVDS / Parallel CMOS |
| Internal Reference | Yes | Yes | Yes | Yes | Yes |
| Operating Temperature | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C |
主な差別化要因
- 105 MSPS sweet spot between 80 and 125 MSPS grades （vs ADS6123IRHBR (80 MSPS) and ADS6125IRHBR (125 MSPS))
- DDR LVDS output minimizes FPGA pin count per channel （vs ADS6122IRHBR (parallel CMOS only))
- Pin-compatible across the ADS612x family （vs ADS6124IRHBR (same die, alternate supplier code))
設計ノート
Place the analog input balun or differential driver as close to the INP/INN pins as possible; keep the two input traces length-matched within 1 mm to preserve SFDR. Split AVDD and DRVDD supplies at the PCB level and decouple each with a 10 uF bulk plus a 100 nF X7R ceramic placed within 3 mm of the supply pin. Route DDR LVDS output pairs with 100-ohm differential impedance and keep length matching within 0.13 mm across each pair.
The 32-VQFN exposed pad MUST be soldered to a continuous ground pour that covers at least 4 square cm of top-layer copper and connects via 25-30 thermal vias (0.2 mm drill, 0.4 mm pitch) to the inner/ground planes. Without this the junction temperature will rise sharply under sustained operation at 105 MSPS, potentially exceeding the 85C ambient rating.
Drive the CLK/CLKB sample-clock input with a low-jitter differential source such as a dedicated clock synthesizer or jitter cleaner; jitter above 0.5 ps rms directly degrades SNR as SNR = 6.02*N + 1.76 + 10*log10(Fs/2*pi*Fin^2) - jitter. For 12-bit performance at 100 MHz IF input, target jitter below 0.3 ps rms to maintain Spurious-Free Dynamic Range headroom.
Do not connect the VCM pin directly to anything other than a DC blocking capacitor to the analog input network - tying VCM to INP/INN will shift bias and reduce linearity. Also ensure RESET is driven to a valid logic level at power-up; leaving it floating can place the device in an undefined state. The MODE pin configuration (CMOS vs DDR LVDS) is latched only at power-up; toggling MODE during operation has no effect.
コンプライアンス情報
RoHS compliant per TI product information. Not AEC-Q100 qualified (commercial/industrial grade, not automotive). Halogen-free status should be confirmed via TI Material Declaration.
