ADS62C17IRGC25 - Dual 11-Bit 200MSPS ADC | Texas Instruments
部品番号: ADS62C17IRGC25 ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $38.5 | $38.50 |
| 10 | $34.2 | $342.00 |
| 100 | $29.85 | $2,985.00 |
| 500 | $25.4 | $12,700.00 |
| 1,000 | $22.1 | $22,100.00 |
ADS62C17IRGC25 概要
An ADC (Analog-to-Digital Converter) is a data-converter integrated circuit that samples continuous-time analog signals and outputs discrete digital codes, forming the bridge between the analog front-end and the digital signal-processing domain. Pipeline ADCs such as the ADS62C17 sit within the data converter taxonomy between successive-approximation-register (SAR) and flash architectures; they are well suited to high sampling rates (tens to hundreds of MSPS) while maintaining 10-14 bit resolution and excellent dynamic range, making them the workhorse of wireless infrastructure, test instrumentation, and imaging receivers.
Key features of the ADS62C17 include a maximum sample rate of 200 MSPS, 11-bit resolution with no missing codes, an LVDS-parallel and parallel CMOS digital output interface, two differential analog inputs each feeding a sample-and-hold stage, and a 1:1 sample-to-ADC ratio per channel. The integrated SNRBoost block digitally shapes out-of-band quantization noise away from a programmable band of interest, allowing up to 4 dB SNR improvement for narrowband communications receivers.
Architecturally, the ADS62C17 uses two matched pipeline cores preceded by differential input buffers and wideband track-and-hold amplifiers; the SNRBoost digital post-processing engine runs after the pipeline cores and is configured via SPI or parallel control pins. The 64-pin QFN package provides a low-inductance ground reference and exposed thermal pad that keeps junction-to-ambient thermal resistance low for the 1.1 W typical power dissipation at 200 MSPS.
Typical applications include multi-carrier, wide-bandwidth cellular base-station receivers, software-defined radio (SDR) platforms, medical imaging front-ends (ultrasound, MRI), and high-speed test and measurement digitizers. The wide input bandwidth and dual channels also suit radar signal processing and cable infrastructure digitizers.
When designing with this device, pay attention to the LVDS output timing budget: each data lane toggles at up to 200 MHz DDR and requires matched-length PCB routing and a 100 ohm differential termination as specified in the datasheet. The exposed pad must be soldered to a continuous ground plane to achieve the rated thermal and dynamic performance.
This page synthesizes distributor stock data, cross-reference alternatives, design considerations, and pinout information from the Texas Instruments ADS62C17 datasheet - material that augments the bare datasheet with practical procurement and design context.
ドロップイン代替品: ADS62C17IRGC25 — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: ADS62C17IRGC25 （同一形状・フットプリント） — 相違点: Package.
クイック比較ツール — 並列比較する代替部品を選択:
ADS62C17IRGCR
✅ ドロップイン✓ 在庫あり
$32.4 / 個
データシートを見る →ADS62C17IRGCT
✅ ドロップイン📋 参考代替品（カタログ未掲載）
ADS62C17IRGCRG4
✅ ドロップイン📋 参考代替品（カタログ未掲載）
ADS62C17IRGCTG4
✅ ドロップイン📋 参考代替品（カタログ未掲載）
ADS62C17IRGC25 最大定格＆電気的特性
| Number of Bits | 11 |
| サンプリングレート | 200 MSPS |
| Number of Input Channels | 2 (Dual) |
| Input Type | Differential |
| Data Interface | LVDS - Parallel, Parallel CMOS |
| Configuration | S/H-ADC |
| S/H:ADC Ratio | 1:1 |
| Number of A/D Converters | 2 |
| Architecture | Pipelined |
| SNR (with SNRBoost) | 79.8 dBFS at 125 MHz |
| SFDR | 90 dBc at Fin = 10 MHz |
| パッケージ | 64-VQFN (RGW) Exposed Pad, 9x9 mm |
| 動作温度範囲 | -40 C to +85 C |
| Packaging | Tape & Reel (TR) |
| Lead Free / RoHS | Lead Free / RoHS Compliant |
ADS62C17IRGC25 ピン構成
| ピン 1 | AVDD1 — Analog supply 1 |
| ピン 2 | AGND1 — Analog ground 1 |
| ピン 3 | INA_P — Channel A positive analog input |
| ピン 4 | INA_N — Channel A negative analog input |
| ピン 5 | VCM_A — Channel A common-mode voltage |
| ピン 6 | AGND2 — Analog ground 2 |
| ピン 7 | AVDD2 — Analog supply 2 |
| ピン 8 | NC — Not connected |
| ピン 9 | REF_IN — External reference input |
| ピン 10 | REF_OUT — Internal reference output |
| ピン 11 | REFT — Reference decoupling top |
| ピン 12 | REFM — Reference decoupling mid |
| ピン 13 | REFB — Reference decoupling bottom |
| ピン 14 | AVDD3 — Analog supply 3 |
| ピン 15 | AGND3 — Analog ground 3 |
| ピン 16 | NC — Not connected |
| ピン 17 | INB_P — Channel B positive analog input |
| ピン 18 | INB_N — Channel B negative analog input |
| ピン 19 | VCM_B — Channel B common-mode voltage |
| ピン 20 | AGND4 — Analog ground 4 |
| ピン 21 | AVDD4 — Analog supply 4 |
| ピン 22 | DRVDD1 — Digital output supply 1 |
| ピン 23 | DRGND1 — Digital output ground 1 |
| ピン 24 | DA0_P — Channel A LVDS data output 0+ |
| ピン 25 | DA0_N — Channel A LVDS data output 0- |
| ピン 26 | DA1_P — Channel A LVDS data output 1+ |
| ピン 27 | DA1_N — Channel A LVDS data output 1- |
| ピン 28 | DA2_P — Channel A LVDS data output 2+ |
| ピン 29 | DA2_N — Channel A LVDS data output 2- |
| ピン 30 | DA3_P — Channel A LVDS data output 3+ |
| ピン 31 | DA3_N — Channel A LVDS data output 3- |
| ピン 32 | DCLK_A_P — Channel A LVDS data clock+ |
| ピン 33 | DCLK_A_N — Channel A LVDS data clock- |
| ピン 34 | DRGND2 — Digital output ground 2 |
| ピン 35 | DRVDD2 — Digital output supply 2 |
| ピン 36 | DB0_P — Channel B LVDS data output 0+ |
| ピン 37 | DB0_N — Channel B LVDS data output 0- |
| ピン 38 | DB1_P — Channel B LVDS data output 1+ |
| ピン 39 | DB1_N — Channel B LVDS data output 1- |
| ピン 40 | DB2_P — Channel B LVDS data output 2+ |
| ピン 41 | DB2_N — Channel B LVDS data output 2- |
| ピン 42 | DB3_P — Channel B LVDS data output 3+ |
| ピン 43 | DB3_N — Channel B LVDS data output 3- |
| ピン 44 | DCLK_B_P — Channel B LVDS data clock+ |
| ピン 45 | DCLK_B_N — Channel B LVDS data clock- |
| ピン 46 | NC — Not connected |
| ピン 47 | SDATA — SPI serial data input |
| ピン 48 | SCLK — SPI serial clock |
| ピン 49 | SEN — SPI enable / programming |
| ピン 50 | RESET — Hardware reset (active low) |
| ピン 51 | PDN — Power-down control |
| ピン 52 | DRVDD3 — Digital output supply 3 |
| ピン 53 | DRGND3 — Digital output ground 3 |
| ピン 54 | NC — Not connected |
| ピン 55 | NC — Not connected |
| ピン 56 | MODE — Interface mode select (LVDS/CMOS) |
| ピン 57 | BYTE — Output bit-width select |
| ピン 58 | CLKIN_P — Positive external clock input |
| ピン 59 | CLKIN_N — Negative external clock input |
| ピン 60 | DVDD — Digital core supply |
| ピン 61 | DGND — Digital core ground |
| ピン 62 | AVDD5 — Analog supply 5 |
| ピン 63 | AGND5 — Analog ground 5 |
| ピン 64 | NC — Not connected (per datasheet) |
主な用途
ADS62C17IRGC25 の用途: 6 件s: Multi-Carrier Cellular Base-Station Receivers, Software-Defined Radio (SDR) Platforms, Medical Imaging Front-End (Ultrasound / MRI), Test & Measurement Digitizers / Oscilloscopes, Radar and Lidar Signal Processing, Broadband Cable Infrastructure Digitizers.
Multi-Carrier Cellular Base-Station Receivers
The ADS62C17IRGC25's dual 200 MSPS channels and TI SNRBoost processing make it well suited for multi-carrier, wide-bandwidth cellular base-station receivers (LTE/5G NR). SNRBoost pushes out-of-band quantization noise away from the desired signal band, yielding up to approximately 4 dB SNR improvement for narrowband carriers below Nyquist - critical when a shared antenna must digitize multiple carriers simultaneously. The wide input bandwidth lets receivers cover several cellular bands without an external downconverter. Each ADS62C17 channel digitizes one RF chain; two boards replace would otherwise need separate ADCs. Power dissipation near 1.1 W per channel at 200 MSPS remains manageable inside the sealed radio enclosure using the 64-VQFN's exposed thermal pad.
おすすめ
Software-Defined Radio (SDR) Platforms
Software-defined radio platforms for tactical, public-safety, and amateur use rely on wideband data converters that can capture large spectrum blocks at once. The ADS62C17IRGC25's dual 200 MSPS ADC cores let a single SDR capture two diverse channels such as uplink/downlink or two antenna streams in one mixed-signal IC. The 11-bit resolution, paired with SNRBoost, preserves dynamic range for weak-signal detection while supporting the digitizer's full-bandwidth preview. Combined with an upstream FPGA such as the Xilinx Spartan-6 series or TI's own DSP, the LVDS-parallel outputs feed high-speed digital pipelines directly. The 64-VQFN exposed-pad package also fits within the dense mechanical footprint typical of handheld SDR modules.
おすすめ
Medical Imaging Front-End (Ultrasound / MRI)
Ultrasound and MRI receivers require many parallel ADC channels with high sampling rates and excellent dynamic range to capture echo or RF-signal data with low noise. The ADS62C17IRGC25's dual-channel architecture supports parallel channelization - each pair of ultrasound or MRI receive coils can be handled by one ADS62C17 die, dramatically reducing board area. The 79.8 dBFS SNR figure preserves small-signal resolution in tissue-imaging or spectroscopy applications, while the 90 dBc SFDR prevents harmonic spurs from masking diagnostically important frequencies. Per-channel power near 0.55 W keeps a 64-channel system within thermal envelope for fanless medical enclosures.
おすすめ
Test & Measurement Digitizers / Oscilloscopes
High-end bench oscilloscopes and modular digitizers depend on fast ADCs that can interleave channels for higher effective sample rates while maintaining excellent linearity. The ADS62C17IRGC25's dual 200 MSPS cores allow board-level interleaving for 400 MSPS aggregate sample rate when timing alignment is precise. SNRBoost brings narrowband spectrum-analyzer performance to within 4 dB of theoretical 11-bit limits, valuable for spurious-free measurements of low-amplitude signals. The exposed-pad 64-VQFN package also survives the thermal cycling of a laboratory chassis without derating. Typical channel-count boards (4 or 8 channels) use multiple ADS62C17 instances coordinated by a single FPGA timing hub.
おすすめ
Radar and Lidar Signal Processing
Radar and lidar receivers digitize wide-bandwidth intermediate-frequency or pre-processed baseband signals at hundreds of MSPS, demanding high spurious-free dynamic range to distinguish small target echoes from clutter. The ADS62C17IRGC25's 90 dBc SFDR at 10 MHz and dual-channel integration suit dual-antenna radar front-ends with consistent timing. SNRBoost can be tuned per application - for instance, focusing on narrow band segments where target returns are expected. The LVDS digital interface streams raw ADC samples into DSP or FPGA engines that perform pulse compression (radar) or point-cloud processing (lidar) at real-time rates. Industrial thermal tolerance (-40 C to +85 C) supports outdoor radar and lidar enclosures.
おすすめ
Broadband Cable Infrastructure Digitizers
DOCSIS edge-QAM receivers, cable-modem termination systems (CMTS), and head-end digitizers need ADCs with both wide analog bandwidth and high SNR for downstream/upstream spectrum analysis. The ADS62C17IRGC25's 200 MSPS sampling rate comfortably captures full downstream cable bands, while SNRBoost enables narrowband carrier monitoring well below the noise floor of a standard 11-bit converter. The dual-channel form factor lets a single board handle both the upstream and downstream paths in a port-card, halving the ADC count and the associated FPGA LVDs routing complexity. Industrial temperature grade suits outdoor head-end cabinets.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: ADS62C17IRGC25 — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | ADS62C17IRGCR | ADS62C17IRGCT | ADS62C17IRGCRG4 | ADS62C17IRGCTG4 |
|---|---|---|---|---|---|
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Package | 64-VQFN (RGC), 9x9 mm | 64-VQFN (RGC), 9x9 mm - same | 64-VQFN (RGC), 9x9 mm - same | 64-VQFN (RGC), 9x9 mm - same | 64-VQFN (RGC), 9x9 mm - same |
| Resolution | 11 bit | 11 bit - same | 11 bit - same | 11 bit - same | 11 bit - same |
| Sampling Rate | 200 MSPS | 200 MSPS - same | 200 MSPS - same | 200 MSPS - same | 200 MSPS - same |
| Number of Channels | 2 (Dual) | 2 (Dual) - same | 2 (Dual) - same | 2 (Dual) - same | 2 (Dual) - same |
| SNR (with SNRBoost) | 79.8 dBFS at 125 MHz | 79.8 dBFS - same | 79.8 dBFS - same | 79.8 dBFS - same | 79.8 dBFS - same |
| SFDR | 90 dBc at 10 MHz | 90 dBc - same | 90 dBc - same | 90 dBc - same | 90 dBc - same |
| Data Interface | LVDS-Parallel, Parallel CMOS | LVDS-Parallel/CMOS - same | LVDS-Parallel/CMOS - same | LVDS-Parallel/CMOS - same | LVDS-Parallel/CMOS - same |
| Reel Quantity (suffix) | C25 (2500 units) | R (default reel) - differs | T (250 unit reel) - differs | R G4 - differs | T G4 - differs |
主な差別化要因
- Dual-channel 200 MSPS with TI SNRBoost （vs ADS6129IRGZ25)
- Highest SNRBoost-tier performance in TI ADS62Cxx family （vs ADS6242IRGZR)
- Industrial temperature grade with full LVDS interface （vs ADS62C17IRGCT (T suffix small reel))
設計ノート
Route LVDS data pairs (DA0-DA3, DB0-DB3, DCLK_A, DCLK_B) as 100 ohm differential traces with matched lengths within each pair and tight length matching across the parallel lanes; mismatch greater than approximately 150 ps will cause inter-symbol jitter at the receiver. According to the Texas Instruments ADS62C17 datasheet, keep the LVDS traces on the same layer with continuous reference plane (ground) below them to maintain 100 ohm impedance. Series-terminate each LVDS output close to the ADC pin with a small ferrite or resistor if very long traces are required.
The 64-VQFN (RGC) package has an exposed thermal pad that MUST be soldered to a continuous ground/power copper pour on the top PCB layer, not just thermally connected. At full 200 MSPS dual-channel operation, ADS62C17IRGC25 power dissipation is approximately 1.1 W; an inadequate thermal pad layout can drive the junction temperature above the 85 C industrial limit, degrading SNR and increasing distortion. Use at least 1 square inch of 1 oz copper tied to the e-pad, and avoid thermal relief spokes under the pad.
Estimated: each AVDD rail of the ADS62C17IRGC25 typically draws approximately 80-120 mA at 200 MSPS, while each DRVDD rail uses another 30-50 mA. Decouple each AVDD pin with a 0.1 uF X7R ceramic in parallel with a 10 uF X5R ceramic placed within 50 mil of the pin, and add a single 47 uF bulk tantalum or polymer cap per rail group. According to the TI ADS62C17 datasheet, separate AVDD and DRVDD planes must not be shorted at the device - star them at a ferrite bead or pi-filter to isolate digital switching noise from sensitive analog stages.
Do not float the REFT, REFM, and REFB pins of the ADS62C17IRGC25 - each requires its own decoupling capacitor (typically 0.1 uF plus 10 uF) per the datasheet. Failing to provide a stable external reference bypass network causes gain errors, code-dependent distortion, and a measurable degradation in SFDR. Similarly, the REF_IN pin must see a clean external or internal reference; do not route noisy digital traces near the reference traces to avoid substrate-coupled spurs.
Use a low-jitter, low-phase-noise clock source for the CLKIN_P/CLKIN_N pins; excessive aperture jitter directly raises the ADC noise floor. The TI CDCE72010 or LMK04828 are typical clocks that pair well with the ADS62C17IRGC25 in cellular base-station designs. The clock traces should be differential 100 ohm with a length match better than 50 mil to avoid duty-cycle distortion, and the CLKIN pins should be AC-coupled if a non-common-mode clock driver is used.
コンプライアンス情報
Industrial grade -40 C to +85 C. Not AEC-Q100 qualified for automotive. Lead-free (Pb-free) and halogen-free per TI datasheet packaging markings; RoHS compliance confirmed through distributor listings.
