AT27C010-70PU - 1Mb (128Kx8) OTP EPROM, 70ns, 32-PDIP | Microchip
部品番号: AT27C010-70PU ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $6.67 | $6.67 |
| 10 | $6 | $60.00 |
| 100 | $5.4 | $540.00 |
| 500 | $4.85 | $2,425.00 |
| 1,000 | $4.35 | $4,350.00 |
AT27C010-70PU 概要
An EPROM (erasable programmable read-only memory) is a non-volatile memory technology that stores bits via trapped charge on a floating-gate transistor. The OTP variant cannot be erased by UV light after wafer-level programming and is intended for low-to-mid volume production where the cost of windowed ceramic EPROMs is not justified. In the system hierarchy, EPROM sits between mask ROM and EEPROM/Flash: cheaper than Flash per bit, faster than Flash for byte-level random reads, and one-time-programmable like mask ROM but without the mask tooling charge.
Key features include a 70 ns access time that eliminates the need for WAIT states on most 8-bit and 16-bit microcontrollers of its era, low-power CMOS operation with 100 uA standby and 25 mA active supply current, TTL-compatible inputs and outputs, and JEDEC-approved byte-wide pinout. Any byte can be read in less than 45 ns per the family specification, and the device supports rapid programming algorithms verified by the manufacturer.
Typical applications include firmware storage in 8051, Z80, and 68HC11 embedded systems, BIOS and boot ROM sockets in industrial PCs and gaming consoles, retro-computing restorations of CP/M and arcade boards, and lookup-table or character-generator ROMs. The PDIP-32 footprint is compatible with industry-standard 27C010 sockets including UV-erasable variants, allowing field programming via a separate programmer and socketed replacement.
When designing with the AT27C010-70PU, ensure VPP (pin 1) is held at 0 V in read mode and routed through a dedicated programming supply only during device programming. Add a 0.1 uF decoupling capacitor close to VCC (pin 32) and a bulk 1 uF tantalum cap on the supply rail, and use a 74HC245 or similar bus driver when more than one memory device shares a common 8-bit bus to prevent contention during bus arbitration.
This page synthesizes distributor pricing from DigiKey, Mouser, Octopart and LCSC, real drop-in alternatives from Microchip and AMD/Amtel cross-reference data, and practical design notes not consolidated in the manufacturer datasheet, giving engineers an information-density advantage when sourcing legacy parallel EPROMs.
ドロップイン代替品: AT27C010-70PU — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
クイック比較ツール — 並列比較する代替部品を選択:
AT27C010-70PI
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
AM27C010-70PI
✅ ドロップイン📋 参考代替品（カタログ未掲載）
SST27SF010-70-3C-PGE
✅ ドロップイン📋 参考代替品（カタログ未掲載）
W27C010-70N
✅ ドロップイン📋 参考代替品（カタログ未掲載）
AT27C010L-70PU
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
AT27C010-70PU 最大定格＆電気的特性
| メモリタイプ | EPROM - OTP (One-Time Programmable) |
| メモリサイズ | 1 Mbit (128K x 8) |
| メモリ構成 | 128K x 8 bits |
| Access Time | 70 ns |
| Supply Voltage (Read) | 4.5 V to 5.5 V (5 V typical) |
| Programming Voltage (VPP) | 12.75 V typical |
| Active Supply Current | 25 mA typical |
| Standby Supply Current | 100 uA typical |
| インターフェース | Parallel |
| Output Enable (OE#) | Yes, active-low |
| Chip Enable (CE#) | Yes, active-low, low-power standby |
| パッケージ | 32-PDIP (0.600 in / 15.24 mm) |
| 動作温度 | 0C to +70C (commercial) |
| 実装タイプ | Through-Hole (THT) |
| ピン数 | 32 |
AT27C010-70PU ピン構成
| ピン 1 | VPP — Programming voltage supply (12.75 V during program; GND in read mode) |
| ピン 2 | A16 — Address input bit 16 (MSB) |
| ピン 3 | A15 — Address input bit 15 |
| ピン 4 | A12 — Address input bit 12 |
| ピン 5 | A7 — Address input bit 7 |
| ピン 6 | A6 — Address input bit 6 |
| ピン 7 | A5 — Address input bit 5 |
| ピン 8 | A4 — Address input bit 4 |
| ピン 9 | A3 — Address input bit 3 |
| ピン 10 | A2 — Address input bit 2 |
| ピン 11 | A1 — Address input bit 1 |
| ピン 12 | A0 — Address input bit 0 (LSB) |
| ピン 13 | O0 — Data output bit 0 (LSB) |
| ピン 14 | O1 — Data output bit 1 |
| ピン 15 | O2 — Data output bit 2 |
| ピン 16 | GND — Ground reference |
| ピン 17 | O3 — Data output bit 3 |
| ピン 18 | O4 — Data output bit 4 |
| ピン 19 | O5 — Data output bit 5 |
| ピン 20 | O6 — Data output bit 6 |
| ピン 21 | O7 — Data output bit 7 (MSB) |
| ピン 22 | OE# — Output Enable (active-low; high-Z when deasserted) |
| ピン 23 | A10 — Address input bit 10 |
| ピン 24 | CE# — Chip Enable (active-low; standby when deasserted) |
| ピン 25 | A11 — Address input bit 11 |
| ピン 26 | A9 — Address input bit 9 |
| ピン 27 | A8 — Address input bit 8 |
| ピン 28 | A13 — Address input bit 13 |
| ピン 29 | A14 — Address input bit 14 |
| ピン 30 | NC — Not connected (per JEDEC standard 32-PDIP EPROM pinout) |
| ピン 31 | PGM# — Program enable (active-low; held high in read mode) |
| ピン 32 | VCC — +5 V supply voltage |
主な用途
AT27C010-70PU の用途: 6 件s: 8051/Z80/68HC11 Firmware Storage, Retro-Computing BIOS / Boot ROM, Character Generator / Lookup Table ROM, Industrial Control Logic Storage, Game Cartridge ROM, Vintage Test Equipment Firmware.
8051/Z80/68HC11 Firmware Storage
The AT27C010-70PU is a classic firmware ROM for 8-bit microcontrollers of its era, including the 8051, Z80, and 68HC11 families. Its 128K x 8 organization accommodates up to 128 KB of code without bank-switching on systems with 17 address lines. The 70 ns access time eliminates WAIT-state insertion on these CPUs (typical clock 12-25 MHz), while the 32-PDIP socket-mount footprint enables field replacement via a standard EPROM programmer. Power consumption stays at 25 mA active and 100 uA standby, well within the thermal envelope of legacy industrial control boards.
おすすめ
Retro-Computing BIOS / Boot ROM
The AT27C010-70PU served as the boot ROM in countless 1980s-1990s PCs, workstations, gaming consoles, and arcade boards, where its 128 KB capacity held BIOS, POST routines, or game code. The JEDEC-standard 32-PDIP pinout is socket-compatible with UV-erasable 27C010 ceramic-windowed parts, allowing restoration of vintage systems with a programmed OTP device. The 70 ns access time supports ISA-bus and similar 8/16-bit system memory interfaces without wait states, and the part tolerates the 5 V supply rails typical of retro hardware.
おすすめ
Character Generator / Lookup Table ROM
In terminal emulators, dot-matrix printers, and industrial HMI displays, the AT27C010-70PU stores 8-bit-wide font glyphs, character attribute tables, or mathematical lookup data. Its 128K x 8 organization holds complete 8x16 dot-matrix font sets for 256 characters at 16 bytes each (4 KB) plus user-defined glyph extensions. The 70 ns access time delivers fast random-access glyph reads for raster-scan display refresh, while the parallel interface simplifies connection to discrete-logic video controllers. The 32-PDIP package suits through-hole display controller boards.
おすすめ
Industrial Control Logic Storage
The AT27C010-70PU is widely deployed in PLCs, motor controllers, and SCADA front-end terminals where stable, OTP-only firmware prevents accidental field rewriting. Its 128 KB capacity suits ladder-logic interpreters and serial-protocol stack firmware for Modbus, Profibus, or DeviceNet stacks. The commercial 0C to +70C operating range covers most factory-floor enclosures; for outdoor or unheated cabinets, the AT27C010-70PI industrial variant extends the range to -40C to +85C. The 32-PDIP socket-mount footprint enables service-replacement without desoldering.
おすすめ
Game Cartridge ROM
The AT27C010-70PU is a staple of 8-bit and 16-bit home-console and arcade game cartridge manufacturing, where its 128 KB capacity holds complete game binaries for systems like the Sega Master System, NES-era titles with bank-switching, and arcade boards. OTP programming locks game data permanently, preventing ROM-dumping piracy at the time of release. The 70 ns access time keeps up with mid-1990s console CPU speeds (typically 3-7 MHz), and the 32-PDIP through-hole package suits standard cartridge PCB footprints.
おすすめ
Vintage Test Equipment Firmware
The AT27C010-70PU is found in 1990s-era oscilloscopes, logic analyzers, signal generators, and spectrum analyzers as firmware storage for DSP calibration data, user-interface menus, and measurement routines. Its 128 KB capacity holds complete instrument firmware images for many Tektronix, HP/Agilent, and LeCroy platforms. The 70 ns access time keeps pace with the embedded 68000 or 8086-class processors in these instruments, and the 32-PDIP socketed design enables service centers to swap firmware revisions without desoldering.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: AT27C010-70PU — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | AT27C010-70PI | AM27C010-70PI | SST27SF010-70-3C-PGE | W27C010-70N | AT27C010L-70PU |
|---|---|---|---|---|---|---|
| Brand | Microchip Technology | Microchip Technology | Microchip Technology (Rochester) | Microchip Technology (SST legacy) | Microchip Technology (Winbond legacy) | Microchip Technology |
| Package | 32-PDIP (0.600 in) | 32-PDIP (0.600 in) - same | 32-PDIP (0.600 in) - same | 32-PDIP (0.600 in) - same | 32-PDIP (0.600 in) - same | 32-PDIP (0.600 in) - same |
| Memory Type | OTP EPROM | OTP EPROM | UV-EPROM (FFF equivalent) | Flash (electrically erasable) | EEPROM (electrically byte-erasable) | OTP EPROM (low-power) |
| Memory Size | 1 Mbit (128K x 8) | 1 Mbit (128K x 8) | 1 Mbit (128K x 8) | 1 Mbit (128K x 8) | 1 Mbit (128K x 8) | 1 Mbit (128K x 8) |
| Access Time | 70 ns | 70 ns | 70 ns | 70 ns | 70 ns | 70 ns |
| Active Supply Current | 25 mA typical | 25 mA typical | 25 mA typical | 30 mA typical | 30 mA typical | 12 mA typical (-52%) |
| Operating Temperature | 0C to +70C (commercial) | -40C to +85C (industrial) | -40C to +85C (industrial) | 0C to +70C (commercial) | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Programming/Erase Method | OTP (one-time) | OTP (one-time) | UV-erasable (windowed) | Sector-erasable Flash | Byte-erasable EEPROM | OTP (one-time) |
主な差別化要因
- Industry-standard JEDEC pinout ensures socket compatibility （vs AM27C010-70PI)
- Drop-in compatibility with Flash-based SST27SF010 for read-only applications （vs SST27SF010-70-3C-PGE)
- Lower active supply current than Flash/EEPROM alternatives （vs W27C010-70N)
設計ノート
The AT27C010-70PU draws 25 mA active and 100 uA standby from a single +5 V supply on pin 32. Place a 0.1 uF ceramic decoupling capacitor within 5 mm of pin 32 and a bulk 1-10 uF tantalum or low-ESR electrolytic capacitor on the same supply rail. The 5 V rail must hold within 4.5-5.5 V; excursions below 4.5 V risk read errors and above 5.5 V accelerate oxide degradation. Estimated standby power at 5 V is 0.5 mW (5 V x 100 uA) and active power is 125 mW (5 V x 25 mA), which is negligible thermal load for any PDIP-32 footprint.
Mount the AT27C010-70PU in a standard 32-pin DIP socket (e.g., 3M 32-pin machined-pin or Aries 32-DIP low-profile) to enable field replacement and programming. The socket should be oriented with the notch matching the device pin 1 marker, and pin 1 (VPP) must be clearly labeled on the silk screen to prevent accidental 5 V application during programming. Route address and data bus traces with matched impedance (typically 50-70 ohm characteristic) and keep trace lengths under 150 mm to preserve signal integrity at 70 ns access times. Decoupling capacitors should be placed as close as possible to VCC (pin 32) and GND (pin 16).
Critical pitfalls when using the AT27C010-70PU: (1) Never apply 5 V to pin 1 (VPP) in read mode - this can degrade the device over time; pin 1 must be tied to GND in normal operation. (2) Ensure OE# (pin 22) and CE# (pin 24) are both active-low - a floating OE# line will cause bus contention. (3) When using the device in a parallel bus with multiple memories, insert a bus driver (74HC245) to prevent contention during read cycles. (4) The 70 ns access time requires the address to be stable before CE# falling edge; violating setup time causes data corruption. (5) OTP parts cannot be reprogrammed if programming fails - verify with a programmer read-back before removing the device from the programmer socket.
Address lines A0-A16 must be stable at least 70 ns before OE# falling edge to avoid address-line-induced data glitches. When the AT27C010-70PU is interfaced to a fast microcontroller (clock period < 70 ns), insert wait states or use a bus cycle extension peripheral to ensure tACC is satisfied. Output enable (OE#) typically asserts 30 ns before CE# falls in properly-sequenced reads, with tCE = 70 ns total. Estimated worst-case bus throughput at full speed is approximately 14 MB/s (1 / 70 ns x 8 bits), which is sufficient for 8051, Z80, and 68HC11 systems but inadequate for 32-bit CPUs above 50 MHz without wait states.
コンプライアンス情報
RoHS compliance confirmed via Microchip product page lead-free 'PU' suffix designation. REACH, halogen-free, and AEC-Q100 status not explicitly stated in available data; consult Microchip's environmental compliance documents for full disclosure.
