DP83TC812S-Q1 - 100BASE-T1 Automotive Ethernet PHY | TI
部品番号: DP83TC812S-Q1 ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $4.95 | $4.95 |
| 10 | $4.46 | $44.60 |
| 100 | $3.85 | $385.00 |
| 500 | $3.42 | $1,710.00 |
| 1,000 | $3.05 | $3,050.00 |
DP83TC812S-Q1 概要
An Ethernet PHY (physical layer transceiver) is the IC that converts digital MAC frames into analog signals suitable for transmission over a physical medium - here, a single unshielded twisted pair. Within the network stack hierarchy (MAC -> PHY -> transformer -> cable), the PHY sits between the media access controller and the single-pair Ethernet (SPE) link, performing encoding, equalization, and clock recovery per the 100BASE-T1 standard.
Key features include Open Alliance TC-10 low-power-mode compliance with less than 30 uA sleep current, passing Level IV emissions with an integrated line filter (LPF), SAE J2962-3 EMC compliance, and configurable MAC-interface I/O voltages of 3.3 V, 2.5 V, and 1.8 V with an optional separate voltage rail for the MAC interface. These attributes make the device suitable for EMC-sensitive automotive harness designs without costly common-mode chokes.
Technically, the DP83TC812S-Q1 is interoperable with both BroadR-Reach PHYs and 100BASE-T1 PHYs, and supports WAKE and sleep signaling per TC-10 for partial-networking power savings. It includes a PRBS frame generator fully compatible with internal loopbacks, allowing link test and ECU validation without a MAC attached.
Typical applications include ADAS camera and radar modules, automotive gateways, infotainment backbone links, and Power-over-Data-Line (PoDL) systems - TI's own PoDL reference design swaps this PHY for the DP83TG720S-Q1 when 1 Gbps is needed.
Design consideration: verify TC-10 wake/sleep state-machine timing against the network master requirements, and keep the configurable MAC rail isolated from the core 1.0 V supply to meet the optional separate-rail feature.
This page synthesizes datasheet facts, drop-in rollover alternatives, comparison tables, and design notes not found in a single manufacturer document.
ドロップイン代替品: DP83TC812S-Q1 — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: DP83TC812S-Q1 （同一形状・フットプリント） — 相違点: Automotive Qualification, MAC Interfaces, Package, Product Type.
クイック比較ツール — 並列比較する代替部品を選択:
DP83TC811S-Q1
✅ ドロップイン📋 参考代替品（カタログ未掲載）
DP83TC812R-Q1
✅ ドロップイン📋 参考代替品（カタログ未掲載）
DP83TC814-Q1
✅ ドロップイン📋 参考代替品（カタログ未掲載）
DP83TG720S-Q1
✅ ドロップイン✓ 在庫あり
$3.85 / 個
データシートを見る →DP83TC812S-Q1 仕様
| Product Type | 100BASE-T1 Automotive Ethernet PHY |
| データレート | 100 Mbps |
| Standards Compliance | IEEE 802.3bw, Open Alliance TC-10, SAE J2962-3 |
| MAC Interfaces | MII, RMII, RGMII, SGMII |
| Configurable I/O Voltages | 3.3 V, 2.5 V, 1.8 V |
| Sleep Current | < 30 uA (TC-10 compliant) |
| EMC Emissions | Level IV pass with integrated LPF |
| Automotive Qualification | AEC-Q100 qualified |
| Interoperability | BroadR-Reach and 100BASE-T1 PHYs |
| Wake Support | WAKE signal per TC-10 |
| Built-in Test | PRBS generator with internal loopbacks |
| パッケージ | VQFN-36, 6.00 mm x 6.00 mm, wettable flank |
| 実装タイプ | Surface Mount |
| Separate MAC Rail | Optional separate voltage rail for MAC interface |
| Orderable Part Number | DP83TC812SRHATQ1 / DP83TC812SRHARQ1 |
DP83TC812S-Q1 vqfn-36, 6.00 mm x 6.00 mm, wettable flank ピン配置ガイド
DP83TC812S-Q1 (vqfn-36, 6.00 mm x 6.00 mm, wettable flank パッケージ) のピン配置。 ピン番号、機能、接続図はメーカーのデータシートで定義されています。正確なフットプリントとはんだ付けのガイドラインについては、データシートを参照してください。
詳細なピン配置データはありません: DP83TC812S-Q1.
詳細は データシート をご参照ください。
主な用途
DP83TC812S-Q1 の用途: 6 件s: Automotive Network Gateway, ADAS Camera and Sensor Modules, Power over Data Lines (PoDL) Nodes, Infotainment and Display Links, Body Electronics and Zonal ECUs, Industrial SPE Retrofit and Test Equipment.
Automotive Network Gateway
Automotive gateways aggregate multiple network domains (CAN, LIN, Ethernet backbone) and need PHYs that survive harsh EMC environments while sipping power when parked. The DP83TC812S-Q1 fits because it passes Level IV EMC emissions with an integrated line filter, reducing external common-mode components, and meets SAE J2962-3 EMC requirements out of the box. Its RGMII and SGMII MAC interfaces connect to high-throughput switch SoCs, while the TC-10 sub-30 uA sleep mode allows the gateway to keep partial-network nodes alive on a budget. Placed between the switch MAC and a single unshielded twisted pair with a 1:1 transformer, the PHY delivers a certified 100 Mbps link; the PRBS generator with internal loopback enables production line testing without a live MAC.
おすすめ
ADAS Camera and Sensor Modules
ADAS camera, radar, and lidar nodes stream constant image or point-cloud data over automotive Ethernet and must wake reliably for every ignition cycle. The DP83TC812S-Q1 is a strong fit: AEC-Q100 qualification covers the under-hood ambient range, the integrated LPF achieves Level IV emissions without a bulky choke in the compact camera housing, and TC-10 sleep below 30 uA preserves battery during long parking periods. Designers typically connect the PHY's RGMII port to the camera SoC or SerDes bridge at a configurable 1.8 V or 2.5 V I/O rail, isolating the MAC supply via the optional separate-rail feature. The wettable-flank VQFN-36 package supports AOI inspection required by automotive assembly lines, and PRBS loopback test modes validate each link at end-of-line.
おすすめ
Power over Data Lines (PoDL) Nodes
TI's automotive PoDL reference design demonstrates a system that powers sensors or actuators over the same single twisted pair used for Ethernet data, and it explicitly supports swapping the DP83TG720S-Q1 for the DP83TC812S-Q1 when 100 Mbps operation is chosen. In this architecture the DP83TC812S-Q1 carries 100BASE-T1 traffic while a PoDL controller injects and extracts DC power on the MDI through coupling networks. The PHY's robust EMC profile (SAE J2962-3, Level IV emissions with integrated LPF) matters because PoDL couples additional inductance and capacitance onto the line. TC-10 wake support is also essential: a PoDL-powered ECU can be woken on demand, keeping the de-energized sleep state under 30 uA as the standard requires.
おすすめ
Infotainment and Display Links
Automotive infotainment head units, cluster displays, and rear-seat entertainment modules use 100BASE-T1 as an inexpensive display and audio transport. The DP83TC812S-Q1 suits this role because its SGMII interface attaches directly to display bridge SoCs, and its interoperability with both BroadR-Reach and 100BASE-T1 PHYs lets one harness mix legacy BroadR-Reach infotainment ECUs with newer 100BASE-T1 nodes. Level IV emissions compliance with the integrated filter is important in the cockpit, where the Ethernet cable often runs adjacent to radio antennas. With configurable 3.3 V, 2.5 V, or 1.8 V I/O voltages, the PHY interfaces to both legacy 3.3 V SoCs and modern 1.8 V display processors without level shifters.
おすすめ
Body Electronics and Zonal ECUs
Zonal architecture pushes computing to the vehicle edge, where body controllers, door modules, and lighting ECUs connect via low-cost single-pair Ethernet. The DP83TC812S-Q1 fits these nodes: TC-10 sleep under 30 uA satisfies always-on battery budgets, the WAKE signal supports network-triggered wake from the central gateway, and the integrated LPF removes the need for discrete filters in low-cost two-layer boards. The DP83TC814-Q1 rollover path lets zonal designers qualify one PCB footprint and populate the 812S for feature-rich nodes or the 814 for commodity I/O modules. PRBS generation with internal loopback enables in-circuit EOL test of each zonal link without requiring a full network stack on the line.
おすすめ
Industrial SPE Retrofit and Test Equipment
Although automotive-qualified, the DP83TC812S-Q1 is used in industrial single-pair Ethernet pilots and 10BASE-T1L/100BASE-T1 test fixtures because 100BASE-T1 signaling matches industrial SPE requirements and TI provides PRBS generators plus loopback modes for link characterization. In test equipment, the PHY's SGMII port feeds FPGA-based traffic generators while the MDI drives the device under test through a standard transformer, letting engineers measure eye diagrams, jitter, and TC-10 wake latency. The sub-30 uA sleep mode also allows battery-powered handheld network testers to poll SPE runs without draining cells. Configurable I/O rails (3.3 V, 2.5 V, 1.8 V) simplify integration with both 5 V-tolerant legacy FPGAs and modern low-voltage SoCs.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: DP83TC812S-Q1 — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | DP83TC811S-Q1 | DP83TC812R-Q1 | DP83TC814-Q1 | DP83TG720S-Q1 |
|---|---|---|---|---|---|
| Package | VQFN-36, 6x6 mm, wettable flank | VQFN-36, 6x6 mm - same | VQFN-36, 6x6 mm - same | VQFN-36, 6x6 mm - same | VQFN-36, 6x6 mm - same |
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Data Rate | 100 Mbps (100BASE-T1) | 100 Mbps | 100 Mbps | 100 Mbps | 1000 Mbps (1000BASE-T1) |
| AEC-Q100 | Qualified | Qualified | Qualified | Qualified | Qualified |
| Interoperability | BroadR-Reach + 100BASE-T1 | BroadR-Reach + 100BASE-T1 | BroadR-Reach + 100BASE-T1 | BroadR-Reach + 100BASE-T1 | 1000BASE-T1 / SGMII SerDes |
主な差別化要因
- SGMII MAC interface for high-end SoC connectivity （vs DP83TC811S-Q1)
- Integrated line filter achieving Level IV emissions （vs DP83TC811S-Q1)
- Common footprint across 100 Mbps and 1 Gbps SPE （vs DP83TG720S-Q1)
設計ノート
The DP83TC812S-Q1 passes Level IV EMC emissions with its integrated line filter, but board-level results depend on a solid, unbroken ground plane under the MDI routing. Keep the single twisted-pair MDI diff pair impedance-controlled at 100 ohms, route it away from clock and switching-regulator nets, and place the 1:1 Ethernet transformer within 25 mm of the PHY pins. TI's SAE J2962-3 compliance was validated with TI reference layouts; deviations in stackup or return paths can degrade emissions by several dB.
Exploit the optional separate MAC-interface voltage rail: power the RGMII/SGMII I/O ring from the host SoC's rail (1.8 V or 2.5 V) while the PHY core uses its own supply. This avoids level shifters and prevents back-powering the SoC when the PHY enters TC-10 sleep (< 30 uA) but the SoC stays powered. Add 100 nF ceramic decoupling at each supply pin and at least 4.7 uF bulk per rail; verify wake transition inrush against your PoDL or always-on rail budget.
When migrating from DP83TC811S-Q1 to DP83TC812S-Q1, do not assume register and strap compatibility - TI publishes the rollover document SNLA340 precisely because reset strap functions and register maps differ. Re-verify LED, boot-strap, and TC-10 wake/sleep state machine configuration against the 812 datasheet before tape-out. For footprint sharing with DP83TG720S-Q1, note that SGMII SerDes pairs require different AC-coupling and reference-clock treatment than the 100 Mbps interfaces.
Use the built-in PRBS generator with internal loopbacks during bring-up and end-of-line test - it transmits and receives without a MAC, letting you validate the full analog link (PHY, transformer, harness) early. Run PRBS at both 100 Mbps and reduced-swing settings to margin the eye; a marginal harness that passes live traffic may still show a nearly closed eye under PRBS, predicting EMC and temperature-corner failures.
コンプライアンス情報
AEC-Q100 qualification and IEEE 802.3bw compliance confirmed per TI datasheet. RoHS/lead-free inferred from TI automotive product page; verify certificate on TI quality portal for the exact orderable suffix.
