DSPIC33FJ128GP206AT-I/PT - 16-bit 40MIPS DSC 128KB Flash | Microchip
部品番号: DSPIC33FJ128GP206AT-I/PT ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $6.12 | $6.12 |
| 10 | $5.72 | $57.20 |
| 100 | $5.31 | $531.00 |
| 500 | $4.95 | $2,475.00 |
| 1,000 | $4.6 | $4,600.00 |
DSPIC33FJ128GP206AT-I/PT 概要
A digital signal controller combines the deterministic control of a microcontroller with the numeric throughput of a DSP. In the product hierarchy, the dsPIC33F sits between general-purpose MCUs (such as the PIC18) and dedicated DSPs, integrating a 16-bit modified Harvard architecture core with DSP engine features - a 17-bit x 17-bit single-cycle hardware multiplier, dual 40-bit accumulators, and a barrel shifter supporting fixed-point arithmetic - making it a natural single-chip choice for digital control loops and signal processing.
Key features include a 16-bit RISC core executing up to 40 MIPS, an 18-channel 10-bit/12-bit analog-to-digital converter capable of up to 500 ksps for multi-channel sensor acquisition, and the GP-series communication suite: multiple UART, SPI, and I2C modules plus the ECAN (CAN 2.0B) controller required in industrial networks and automotive-adjacent systems. Flash is self-programmable for field firmware updates, and the device supports In-Circuit Serial Programming (ICSP) and debugging via any PGECx/PGEDx pin pair.
The modified Harvard architecture keeps instruction and data buses separate, allowing simultaneous fetch of instruction and operands, which underpins the single-cycle MAC (multiply-accumulate) operation essential to digital filters and PID loops. Peripheral Pin Select (PPS) on this family gives designers flexibility to map digital peripherals onto 53 I/O pins, simplifying PCB routing. The industrial temperature grade (-40C to +85C) and tape-and-reel packaging support automated high-volume assembly.
Typical applications include motor control (BLDC, PMSM FOC), digital power supplies and inverters, industrial automation sensing nodes, and audio signal processing where the ADC-DSP-DAC chain processes signals deterministically.
Design consideration: the device requires a stable 3.0 V-3.6 V rail; take care that ECAN transceivers and ADC reference integrity justify dedicated low-noise supply decoupling at each VDD/VSS pair.
This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet.
ドロップイン代替品: DSPIC33FJ128GP206AT-I/PT — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: DSPIC33FJ128GP206AT-I/PT （同一形状・フットプリント） — 相違点: Package, Core Architecture, Programming Interface, Operating Temperature, RoHS Status.
クイック比較ツール — 並列比較する代替部品を選択:
DSPIC33FJ128GP206A-I/PT
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
DSPIC33FJ128GP206T-I/PT
✅ ドロップイン✓ 在庫あり
$4.89 / 個
データシートを見る →DSPIC33FJ128GP206AT-E/PT
✅ ドロップイン📋 参考代替品（カタログ未掲載）
DSPIC33FJ128GP206AT-I/PT 最大定格＆電気的特性
| Core | dsPIC33F 16-bit |
| MIPS | 40 MIPS |
| Flash Program Memory | 128 KB (128K x 8) |
| RAM | 8 KB (8K x 8) |
| I/O Pins | 53 |
| Operating Voltage | 3.0 V to 3.6 V |
| ADC | 18-channel 10-bit/12-bit |
| パッケージ | 64-TQFP (10x10 mm) |
| Terminal Pitch | 0.5 mm |
| 実装タイプ | Surface Mount |
| 動作温度 | -40C to +85C (Industrial) |
| Technology | CMOS |
| DSP Features | 17x17 hardware multiplier, barrel shifter, fixed-point DSP engine |
| Communication Interfaces | UART, SPI, I2C, ECAN (CAN 2.0B) |
| Programming | ICSP (PGECx/PGEDx pairs) |
| Packaging | Tape & Reel (T&R) |
DSPIC33FJ128GP206AT-I/PT 64-tqfp (10x10 mm) ピン配置ガイド
DSPIC33FJ128GP206AT-I/PT (64-tqfp (10x10 mm) パッケージ) のピン配置。 このデジタルICには、GPIO、通信インターフェース (UART、SPI、I2C)、および電源ピンが含まれています。代替ピン機能と設定オプションについては、メーカーのデータシートを参照してください。組み込みシステム設計とPCBレイアウトに不可欠です。
詳細なピン配置データはありません: DSPIC33FJ128GP206AT-I/PT.
詳細は データシート をご参照ください。
主な用途
DSPIC33FJ128GP206AT-I/PT の用途: 6 件s: Motor Control (BLDC / PMSM FOC), Digital Power Supplies and Inverters, Industrial Automation and Sensing Nodes, Audio and Speech Signal Processing, Embedded Control with CAN Networking (ECAN), Test, Measurement and Instrumentation.
Motor Control (BLDC / PMSM FOC)
The DSPIC33FJ128GP206AT-I/PT is purpose-built for digital motor control: its 40 MIPS 16-bit DSP engine with a 17x17 single-cycle hardware multiplier and dual 40-bit accumulators executes field-oriented control (FOC) algorithms for BLDC and PMSM motors with deterministic loop timing. The 18-channel 10-bit/12-bit ADC samples phase currents and the DC bus at high speed, feeding current-loop bandwidths in the several-kHz range. With 53 I/O pins and ECAN on-board, the same chip can drive a three-phase inverter and report telemetry on a CAN network. Place it between current-sense conditioning and the gate-driver stage; the fixed-point DSP core adds no switching jitter compared to a software-only MCU solution.
おすすめ
Digital Power Supplies and Inverters
In digitally controlled AC/DC and DC/DC power stages, the DSPIC33FJ128GP206AT-I/PT closes voltage and current loops at high update rates using its 40 MIPS core and hardware MAC, implementing average-current-mode or peak-current-mode control in firmware. The high-speed 18-channel ADC samples output voltage, inductor current, and temperature simultaneously, while PWM peripherals generate the switching waveforms. The 3.0 V-3.6 V supply range matches standard controller rails, and the ECAN module enables PMBus-style supervision in parallel inverter systems. Compared to analog-only control, the DSP approach allows soft-start profiles, non-linear gain scheduling, and firmware upgradability via the self-programmable 128 KB Flash.
おすすめ
Industrial Automation and Sensing Nodes
Factory automation nodes benefit from the DSC's combination of analog acquisition and industrial networking: the 18-channel ADC digitizes multiple sensors (pressure, temperature, position) through a single controller, DSP routines perform filtering and linearization in firmware, and the ECAN controller plus multiple UART/SPI/I2C modules connect the node to PLC backplanes and HMI panels. The -40C to +85C industrial temperature rating and 53 configurable I/O with Peripheral Pin Select simplify routing on crowded PCBs. Running PID and FFT-based condition-monitoring on the 40 MIPS core removes the need for a separate signal-processor chip, cutting BOM cost in high-volume sensor and actuator modules.
おすすめ
Audio and Speech Signal Processing
The GP-series dsPIC33F excels in embedded audio: its single-cycle MAC and barrel shifter execute FIR/IIR filters, sample-rate converters, and speech codecs at 40 MIPS, while the 12-bit ADC digitizes microphone inputs for voice-band processing. With 128 KB of Flash, codec tables and coefficient sets reside on-chip, and the 8 KB RAM buffers multiple audio frames for block processing. UART/I2C interfaces connect to external audio codecs or DACs. Designers should budget the ADC resolution (up to 12-bit) for voice-quality rather than hi-fi applications, and use the DSP X/Y memory architecture to sustain overlapped MAC operations without pipeline stalls.
おすすめ
Embedded Control with CAN Networking (ECAN)
For nodes that must live on a CAN 2.0B bus - automotive-adjacent accessories, medical carts, building controllers - the on-chip ECAN module of the DSPIC33FJ128GP206AT-I/PT provides full CAN 2.0B compliance with hardware message buffering, offloading the 40 MIPS core from bit-level protocol handling. Multiple UARTs, SPI, and I2C modules bridge legacy sensors into the CAN network, and Peripheral Pin Select lets the designer place ECAN and UART pins optimally for PCB layout across the 53 I/O. Firmware updates over the bus are practical because the 128 KB Flash is self-programmable, enabling field maintenance without physical access.
おすすめ
Test, Measurement and Instrumentation
Bench instruments and portable measurement tools use the DSPIC33FJ128GP206AT-I/PT as a real-time acquisition engine: the 18-channel ADC captures multiple signals for simultaneous sampling, DSP firmware performs averaging, windowing, and FFT analysis on the 40 MIPS core, and results stream over UART/USB-bridge UART links to a host. The self-programmable Flash supports calibration data storage and firmware feature updates in the field, while the industrial temperature grade suits both lab and factory-floor instruments. Designers should allocate low-noise 3.3 V decoupling per VDD/VSS pair to preserve the ADC's effective resolution, and use the multiple PGECx/PGEDx pairs for production programming on assembled boards.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: DSPIC33FJ128GP206AT-I/PT — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | DSPIC33FJ128GP206A-I/PT | DSPIC33FJ128GP206T-I/PT | DSPIC33FJ128GP206AT-E/PT |
|---|---|---|---|---|
| Package | 64-TQFP (10x10 mm) | 64-TQFP (10x10 mm) - same | 64-TQFP (10x10 mm) - same | 64-TQFP (10x10 mm) - same |
| Brand | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology |
| Core / MIPS | dsPIC33F 16-bit / 40 MIPS | dsPIC33F 16-bit / 40 MIPS | dsPIC33F 16-bit / 40 MIPS | dsPIC33F 16-bit / 40 MIPS |
| Flash / RAM | 128 KB / 8 KB | 128 KB / 8 KB | 128 KB / 8 KB | 128 KB / 8 KB |
| Operating Voltage | 3.0 V to 3.6 V | 3.0 V to 3.6 V | 3.0 V to 3.6 V | 3.0 V to 3.6 V |
| Temperature Grade | Industrial (-40C to +85C) | Industrial (-40C to +85C) | Industrial (-40C to +85C) | Extended (higher ceiling) |
| Silicon Revision / Errata | AT revision | Latest A revision (errata fixed) | Non-A revision (per FindIC) | AT revision, extended temp |
| I/O / ADC | 53 I/O / 18-ch 10/12-bit | 53 I/O / 18-ch 10/12-bit | 53 I/O / 18-ch 10/12-bit | 53 I/O / 18-ch 10/12-bit |
主な差別化要因
- Latest silicon revision with errata fixes （vs DSPIC33FJ128GP206T-I/PT)
- Extended-temperature option at identical footprint （vs DSPIC33FJ128GP206AT-E/PT)
- DSP engine differentiates from plain MCUs （vs DSPIC33FJ128GP206A-I/PT)
設計ノート
Supply the device from a single 3.0 V-3.6 V rail (nominal 3.3 V). Estimated: a 40 MIPS dsPIC33FJ draws on the order of 40-60 mA plus I/O load, so a 100 mA-class LDO such as the MCP1702 with 1 uF ceramic capacitors at every VDD/VSS pair is a workable baseline. If the ADC is used for precision sampling, add an RC or ferrite filter between the digital rail and AVDD to preserve effective resolution.
The 64-TQFP has a 0.5 mm pitch - specify a 4-mil (0.1 mm) minimum solder-mask opening and follow IPC-compliant land patterns for the 10x10 mm footprint. Place 100 nF decoupling capacitors within 2-3 mm of each VDD pin pair, and keep the ECAN/UART routing away from the ADC analog traces. Expose a solid ground plane on layer 2 to minimize return-path loops for the 40 MHz system clock.
Programming requires matched PGECx/PGEDx pairs - per Microchip documentation, the dsPIC33FJ128GP206 has more than one pair and any pair may be used, but ICSPCLK and ICSPDAT must come from the same pair (e.g., PGEC2 with PGED2). Mixing pins from different pairs is a common bring-up failure. Also note this is a 3.3 V device: never drive its I/O directly from 5 V logic without level translation, and verify the silicon errata sheet for your exact revision before production.
コンプライアンス情報
RoHS/lead-free status inferred from standard Microchip current-production packaging and distributor listings; REACH and halogen-free status not stated in the provided data.
