Intel の EP1S20B672C7N - Stratix FPGA, 18,460 LEs, 672-BGA | Intel EP1S20B672C7N - 電子部品
Intel

EP1S20B672C7N - Stratix FPGA, 18,460 LEs, 672-BGA | Intel

部品番号: EP1S20B672C7N ✗ 生産終了
在庫あり 1〜3営業日以内に発送
1.5 V Vdss 672-BBGA (Fine-pitch BGA, 35 × 35 mm, 1.27 mm pitch) Package -7 Speed 1,669,248 bits Memory
開始価格 $320 USD / 個
MOQ: 1 |
価格更新日: 2026-09-06
ボリューム価格
数量 単価 小計
1 $501.6 $501.60
10 $481.5 $4,815.00
100 $425 $42,500.00
500 $372 $186,000.00
1,000 $320 $320,000.00
ℹ️ すべての価格はUSDです
データシートを見る (PDF) 代替品を見る

EP1S20B672C7N 概要

The Intel (formerly Altera) EP1S20B672C7N is a member of the original Stratix FPGA family, fabricated on a 0.13 µm CMOS process and housed in a 672-ball BGA package (35 × 35 mm, 1.27 mm pitch). It integrates 18,460 logic elements across 1,846 LABs/CLBs, 1,669,248 bits of embedded memory, and 426 user I/O pins, providing a high-density programmable platform for ASIC prototyping, communications infrastructure, and signal-processing pipelines.

What is an FPGA? A Field-Programmable Gate Array (FPGA) is a semiconductor IC containing configurable logic blocks (CLBs/LABs), programmable interconnect, and dedicated hard IP such as block RAM, DSP blocks, PLLs, and transceivers. FPGAs sit in the programmable logic tier of the digital hierarchy, between fixed-function ASICs and software-driven processors, and are valued for parallel computation, deterministic latency, and in-field reconfigurability.

Key features of the EP1S20B672C7N include 1,669,248 RAM bits distributed across TriMatrix memory blocks (true dual-port RAM up to 512 Kbits per block), dedicated DSP blocks for high-speed multiply-accumulate operations, and up to 12 embedded PLLs per device for clock synthesis. The device supports 426 user I/Os across multiple I/O banks with selectable LVDS, LVCMOS, SSTL, and HSTL standards, and offers dedicated 1.5 V core supply operation.

Architecturally, the Stratix family introduced the LUT-based logic element, the TriMatrix hierarchical memory architecture, and embedded DSP blocks with hardware multipliers - innovations that defined subsequent Cyclone and Arria lines. The C7N speed/temperature grade indicates a -40 °C to 85 °C commercial-extended operating range with a -7 speed bin, balancing timing margin against density.

Typical applications include ASIC prototyping, software-defined radio, digital video and image processing, telecom line-card packet processing, and high-speed serial interface bridging. Engineers also deploy EP1S20B672C7N in industrial motion control and military/aerospace systems where MIL-STD-810 qualification of equivalent Stratix variants is desirable.

When designing with this part, ensure robust thermal management for the 35 × 35 mm BGA - theta-JA values for large BGA packages typically require forced airflow or large ground-plane copper pours to stay within the 0 °C to 85 °C junction range. Power sequencing of the 1.5 V core, auxiliary supplies, and I/O bank VCCIO rails must follow the Stratix handbook reference to avoid in-rush latch-up.

This page synthesizes distributor pricing, drop-in alternative sourcing, and PCB-layout guidance beyond what the manufacturer datasheet alone provides.

ドロップイン代替品: EP1S20B672C7N — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。

このシリーズのバリエーション

同一シリーズでドロップイン互換のモデル: EP1S20B672C7N （同一形状・フットプリント） — 相違点: Operating Temperature, Package, Speed Grade, Configuration Method, Family.

Intel
Operating Temperature: 0 C to 85 C (commercial)
Package: 672-ball FineLine BGA (672-BBGA)
Speed Grade: C6
比較対象 EP1S20B672C7N →
Intel
Operating Temperature: 0 C to +85 C (Commercial)
Package: 672-ball BGA (672-BBGA), 35 x 35 mm, 1.27 mm pitch
Speed Grade: 6
比較対象 EP1S20B672C7N →
Intel
Operating Temperature: 0 C to 85 C (commercial)
Package: 672-BBGA (FineLine BGA) 35 x 35 mm
Speed Grade: -6
比較対象 EP1S20B672C7N →
Intel
Operating Temperature: 0C to 85C (commercial)
Package: 672-ball FineLine BGA (35 x 35 mm, 1.27 mm pitch)
Speed Grade: C7
比較対象 EP1S20B672C7N →
Intel
Operating Temperature: 0°C to +85°C (commercial)
Package: 672-FBGA (FineLine BGA)
Speed Grade: C7 (-7)
比較対象 EP1S20B672C7N →
Intel
Operating Temperature: -40C to +85C (industrial grade, I7 suffix)
Package: 672-BBGA (FineLine BGA), 35 x 35 mm, 1.27 mm pitch
Family: Stratix (first generation)
比較対象 EP1S20B672C7N →
Intel
Operating Temperature: 0 C to 85 C
Package: 672-BGA, 35 x 35 mm, 1.27 mm pitch
Speed Grade: C7 (commercial, slowest bin)
比較対象 EP1S20B672C7N →
Intel
Operating Temperature: 0 °C to 85 °C (Commercial)
Configuration Method: SRAM-based, JTAG (IEEE 1149.1)
Family: Stratix
比較対象 EP1S20B672C7N →
Altera
Operating Temperature: 0 °C to 85 °C (commercial)
Package: 672-BBGA (FineLine BGA), 35 × 35 mm, 1.27 mm pitch
Configuration Method: JTAG / Passive Serial / Active Serial
比較対象 EP1S20B672C7N →

クイック比較ツール — 並列比較する代替部品を選択:

EP1S25F672C7N

✅ ドロップイン ⚠️ 仕様未検証
Altera
📦 672-BBGA (Fine-pitch BGA, 35 × 35 mm, 1.27 mm pitch)
Stratix · 25,660 · 2,566 · 1,944,576 · 473 · 672 (BGA balls) · 672-BBGA (FineLine BGA), 35 × 35 mm, 1.27 mm pitch · 0.13 µm CMOS

✓ 在庫あり

$535 / 個

データシートを見る →

EP1S25B672C7N

✅ ドロップイン ⚠️ 仕様未検証
Intel
📦 672-BBGA (Fine-pitch BGA, 35 × 35 mm, 1.27 mm pitch)
Stratix · 25660 · 473 · 672 · 672-BGA (BBGA), 35 x 35 mm, 1.27 mm pitch · 0 °C to 85 °C (Commercial) · 1.5 V · CMOS

✓ 在庫あり

$620.15 / 個

データシートを見る →

EP1S20F672C7N

✅ ドロップイン ⚠️ 仕様未検証
Intel
📦 672-BBGA (Fine-pitch BGA, 35 × 35 mm, 1.27 mm pitch)
Stratix (first generation) · Stratix · 18,460 · 18,460 · 2,132 · 1,669,248 bits (426 Kbit total) · 56 (dedicated 18x18 multipliers) · 586

✓ 在庫あり

$109.2 / 個

データシートを見る →

EP1S20B672C6N

✅ ドロップイン ⚠️ 仕様未検証
Intel
📦 672-BBGA (Fine-pitch BGA, 35 × 35 mm, 1.27 mm pitch)
Stratix · EP1S20 · 18,460 · 1,846 · 1,669,248 bits · 426 · 130 nm CMOS · 1.5 V

✓ 在庫あり

$425 / 個

データシートを見る →

EP1S10B672C7N

✅ ドロップイン ⚠️ 仕様未検証
Intel
📦 672-BBGA (Fine-pitch BGA, 35 × 35 mm, 1.27 mm pitch)
Intel / Altera · Stratix · CMOS · 10570 cells · 420.17 MHz · 1.5 V · 130 nm · BGA

✓ 在庫あり

$67.9 / 個

データシートを見る →

EP1S20B672C7N 最大定格＆電気的特性

Series Stratix
Family Stratix (original)
Process Technology 0.13 µm CMOS
Logic Elements (LEs) 18,460
LABs / CLBs 1,846
Embedded Memory Bits 1,669,248 bits
Maximum User I/O 426
Number of Pins / Balls 672
Package Type 672-BBGA (Fine-pitch BGA, 35 × 35 mm, 1.27 mm pitch)
Supply Voltage (Core, VCCINT) 1.5 V
動作温度 0 °C to 85 °C (Commercial Extended)
Speed Grade -7
実装タイプ Surface Mount (BGA)
MSLレベル 3 (per JEDEC J-STD-020)
Logic Family CMOS

EP1S20B672C7N 672-bbga (fine-pitch bga, 35 × 35 mm, 1.27 mm pitch) ピン配置ガイド

EP1S20B672C7N (672-bbga (fine-pitch bga, 35 × 35 mm, 1.27 mm pitch) パッケージ) のピン配置。 このデジタルICには、GPIO、通信インターフェース (UART、SPI、I2C)、および電源ピンが含まれています。代替ピン機能と設定オプションについては、メーカーのデータシートを参照してください。組み込みシステム設計とPCBレイアウトに不可欠です。

EP1S20B672C7N の 672-bbga (fine-pitch bga, 35 × 35 mm, 1.27 mm pitch) パッケージピン配置図

詳細なピン配置データはありません: EP1S20B672C7N.

詳細は データシート をご参照ください。

主な用途

EP1S20B672C7N の用途: 6 件s: ASIC Prototyping & Emulation, Software-Defined Radio Baseband, Telecom Line-Card Packet Processing, Digital Video & Image Processing, Industrial Motion Control & Robotics, High-Speed Serial Interface Bridging.

🖥️

ASIC Prototyping & Emulation

The EP1S20B672C7N's 18,460 logic elements, 1,669,248 bits of TriMatrix block RAM, and 426 user I/O pins make it a capable platform for ASIC prototyping and pre-silicon validation. Engineers map RTL onto the Stratix LUT fabric, the on-chip memory models FIFOs and register files, and the 426 I/Os partition the design across multiple packages for multi-FPGA emulation. Compared to ASIC tapeout, the FPGA prototype reduces verification cost by orders of magnitude while preserving near-ASIC timing behavior at the -7 speed grade.

おすすめ

EP1S25F672C7N · Altera EP1S20F672C7N · Intel
🌐

Software-Defined Radio Baseband

The EP1S20B672C7N integrates dedicated DSP blocks with hardware multipliers that accelerate the multiply-accumulate operations central to SDR baseband processing. The 426 user I/Os include LVDS pairs for ADC/DAC sample interfaces, while 1.67 Mbits of block RAM buffers IQ samples between the RF front-end and demodulation logic. With parallel DSP throughput the device handles moderate-bandwidth waveforms, though newer Cyclone V or Arria 10 FPGAs with integrated transceivers are preferred for wideband designs.

おすすめ

EP1S25F672C7N · Altera EP1S10B672C7N · Intel
📡

Telecom Line-Card Packet Processing

The EP1S20B672C7N was widely deployed in telecom line cards for packet classification, queuing, and forwarding at wire speed. Its 1.67 Mbits of on-chip memory store route lookup tables, the 426 I/Os connect to network processors and switch fabrics via UTOPIA/SPI-4.2, and the deterministic LUT-based fabric gives predictable latency critical for QoS scheduling. The 672-BGA package exposes enough I/O bandwidth to drive multiple Gigabit Ethernet ports in parallel.

おすすめ

EP1S25F672C7N · Altera
📺

Digital Video & Image Processing

The EP1S20B672C7N's parallel LUT fabric and embedded DSP blocks accelerate real-time video processing pipelines such as motion estimation, deinterlacing, and color-space conversion. The 1,669,248 bits of block RAM store multiple video frames as line buffers, while the 426 user I/Os accept parallel DVI/HDMI pixel streams and drive DDR memory controllers. Compared to a CPU/GPU, the FPGA's deterministic per-pixel latency avoids jitter in broadcast workflows.

おすすめ

EP1S25F672C7N · Altera
🏭

Industrial Motion Control & Robotics

The EP1S20B672C7N executes multi-axis PID control loops, trajectory generation, and EtherCAT / SERCOS interface logic on a single chip. Its 426 I/Os accept quadrature encoder feedback and drive PWM outputs, the DSP blocks accelerate Park/Clarke transforms for field-oriented motor control, and the deterministic LUT fabric guarantees sub-microsecond loop time at the -7 speed grade. The commercial-extended temperature range (0 °C to 85 °C) suits most factory-floor enclosures.

おすすめ

EP1S25F672C7N · Altera EP1S20B672C6N · Intel
🌐

High-Speed Serial Interface Bridging

The EP1S20B672C7N bridges between legacy parallel buses (PCI, UTOPIA, SPI-4.2) and modern high-speed serial links by running soft PHYs in the LUT fabric. The 1.67 Mbits of block RAM stage packets between clock domains, and the 426 user I/Os expose enough LVDS pairs to drive multiple multi-gigabit transceivers via external PHY devices. Although the Stratix I lacks native transceivers, the LUT/IO count makes it a viable bridge for protocol conversion at moderate data rates.

おすすめ

EP1S25F672C7N · Altera

おすすめ製品の概要

EP1S25F672C7N Altera 使用用途: ASIC Prototyping & Emulation, Software-Defined Radio Baseband, Telecom Line-Card Packet Processing, Digital Video & Image Processing, Industrial Motion Control & Robotics, High-Speed Serial Interface Bridging EP1S20F672C7N Intel 使用用途: ASIC Prototyping & Emulation EP1S10B672C7N Intel 使用用途: Software-Defined Radio Baseband EP1S20B672C6N Intel 使用用途: Industrial Motion Control & Robotics
What is the logic element count of EP1S20B672C7N?
The EP1S20B672C7N integrates 18,460 logic elements (LEs) organized into 1,846 LABs/CLBs. According to the Altera Stratix Device Family Data Sheet, each LE contains a 4-input look-up table, a programmable register, and dedicated carry-chain logic, giving the part the equivalent density of a small ASIC. This makes it suitable for ASIC prototyping and mid-range DSP pipelines.
How much embedded memory does EP1S20B672C7N provide?
The EP1S20B672C7N contains 1,669,248 bits of on-chip memory in the Stratix TriMatrix architecture, comprising M512 (32 × 18), M4K (128 × 36), and M-RAM (4 K × 144) block RAMs. This provides true dual-port RAM up to 512 Kbits per block, enabling FIFO buffers, lookup tables, and on-chip data caches without external SRAM.
What package does EP1S20B672C7N use?
The EP1S20B672C7N is packaged in a 672-ball Fine-pitch BGA measuring 35 × 35 mm with a 1.27 mm ball pitch, designated the BGA-672 or 672-BBGA form factor. This large BGA supports 426 user I/O pins distributed across multiple I/O banks with selectable LVDS, LVCMOS, SSTL, and HSTL standards for interfacing with DDR memories, parallel buses, and high-speed LVDS links.
Is EP1S20B672C7N obsolete?
Yes. The EP1S20B672C7N is listed as obsolete by Altera/Intel. The original Stratix family has been superseded by Stratix II/III/IV/V/10, and long-term production has ended. According to DigiKey, the part is offered from remaining stock or authorized aftermarket distributors, with the part not recommended for new designs (NRND has progressed to full obsolete status).
What core voltage does EP1S20B672C7N require?
The EP1S20B672C7N operates from a 1.5 V core supply (VCCINT) with auxiliary supplies for PLL analog blocks and programmable I/O bank VCCIO rails (typically 1.5 V, 1.8 V, 2.5 V, or 3.3 V depending on I/O standard). The Stratix handbook mandates a specific power-on sequence to avoid in-rush latch-up; check the Stratix Power-Up Sequence app note before PCB bring-up.
Where to buy EP1S20B672C7N at the lowest price?
As of 2026-09-07, the EP1S20B672C7N unit price is approximately $501.60 at quantity 1 per Heisener.com, with inventory of 5,792 pieces. Cross-check DigiKey, Mouser, and Xecor; due to obsolete status, authorized distributors carry only surplus stock and pricing varies widely. For cost-sensitive programs consider migrating to a Cyclone III/IV equivalent rather than redesigning around EP1S20.
What is the lead time for EP1S20B672C7N?
The lead time for EP1S20B672C7N is generally Can Ship Immediately for small quantities from distributors such as Heisener (in stock as of 2026-09-07). For larger production volumes, expect lead times of 4-12 weeks as stock depends on authorized aftermarket channels, with no manufacturer production resumption available. Independent distributors may quote shorter or longer lead times depending on lot availability.
EP1S20B672C7N vs EP1S25F672C7 - which is better for ASIC prototyping?
The EP1S20B672C7N provides 18,460 LEs and 1.67 Mbits RAM, while the EP1S25F672C7 delivers 25,660 LEs and approximately 1.92 Mbits RAM in the same 672-BGA package, making the S25 a drop-in density upgrade. Choose EP1S25F672C7 if your design exceeds 18k LEs; choose EP1S20B672C7N only when surplus inventory cost matters more than density headroom.
What is the best drop-in replacement for EP1S20B672C7N?
The best drop-in replacement is the EP1S25F672C7N in the same 672-BGA package with 39 % more logic elements (25,660 vs 18,460 LEs). For migration to a current-generation device, Cyclone III EP3C120F780C7N or Stratix III EP3SL50F780C7N require PCB redesign (different package). The C7 speed grade is the same across EP1S20/EP1S25, preserving timing margin.
When should I choose EP1S20B672C7N over a Cyclone IV equivalent?
Choose the EP1S20B672C7N over a Cyclone IV when you need its dedicated TriMatrix memory architecture, embedded DSP blocks, and Stratix-class routing - features Cyclone IV cannot match. For new designs, however, prefer Cyclone III/IV due to active production, lower cost, and modern Quartus support. EP1S20B672C7N is best reserved for maintaining legacy designs already in production.
Is EP1S20B672C7N suitable for software-defined radio applications?
Yes, the EP1S20B672C7N is suitable for software-defined radio (SDR) baseband processing due to its dedicated DSP blocks with hardware multipliers, 426 user I/Os for LVDS sample interfaces, and parallel DSP throughput. The 1.67 Mbit on-chip memory buffers sample data between ADC/DAC interfaces. For modern wideband SDR, however, Cyclone V or Arria 10 devices with integrated transceivers are preferred.
Where to download EP1S20B672C7N datasheet PDF?
The official EP1S20B672C7N datasheet is contained in the Altera Stratix Device Family Data Sheet, available at https://www.altera.com/literature/hb/stx/stratix_handbook.pdf. The Stratix handbook provides detailed electrical characteristics, timing models, and pinout tables. For device-specific ordering information, consult the Altera (now Intel) FPGA Product Catalog. Always refer to the latest revision before committing to a design.
Where to find EP1S20B672C7N pinout and ball map?
The EP1S20B672C7N pinout for the 672-BGA package is documented in the Stratix Device Family Data Sheet Chapter 8 (Pin Connection Guidelines) and Chapter 9 (Pin-Out Tables). The pin assignment file (.pin) is also available through the Quartus II Pin Planner once the EP1S20B672C7N device is selected. Always validate your pinout against the specific device package datasheet, not just the family datasheet.
What are the key specifications of EP1S20B672C7N that engineers should know?
The EP1S20B672C7N key specifications are: 18,460 logic elements in 1,846 LABs, 1,669,248 RAM bits in TriMatrix blocks, 426 maximum user I/O, 672-ball BGA at 35 × 35 mm with 1.27 mm pitch, 1.5 V core supply, 0 °C to 85 °C commercial-extended temperature range, and -7 speed grade. It is built on a 0.13 µm CMOS process and is currently listed as obsolete by Intel.

エンジニアリング参考データ: EP1S20B672C7N — 比較、設計ガイダンス、コンプライアンス情報。

選定ガイド

Choose the EP1S20B672C7N when you need a mid-density 18,460-LE Stratix FPGA in the 672-BGA package for legacy designs already in production or for ASIC prototyping where Quartus II support is sufficient. For new designs, prefer Cyclone III or Cyclone IV devices because of active production, lower cost, and modern Quartus Prime support. If your design exceeds 18k LEs, choose the EP1S25F672C7N drop-in upgrade in the same 672-BGA footprint. For cost reduction in a smaller design, the EP1S10B672C7N provides 10,570 LEs in the identical package. All five listed alternatives share the same 672-BGA package, preserving PCB layout for drop-in replacement.

代替品との比較

パラメータ この製品 EP1S25F672C7N EP1S25B672C7N EP1S20F672C7N EP1S20B672C6N EP1S10B672C7N
Brand Intel (formerly Altera) Intel Intel Intel Intel Intel
Package 672-BBGA (35 × 35 mm, 1.27 mm pitch) 672-BBGA (same) 672-BBGA (same) 672-BBGA (same) 672-BBGA (same) 672-BBGA (same)
Logic Elements 18,460 25,660 (+39 %) 25,660 (+39 %) 18,460 (same die) 18,460 (same) 10,570 (-43 %)
Embedded Memory (bits) 1,669,248 1,944,576 (+16 %) 1,944,576 (+16 %) 1,669,248 (same) 1,669,248 (same) 920,448 (-45 %)
Maximum User I/O 426 426 (same) 426 (same) 426 (same) 426 (same) 346 (-19 %)
Speed Grade -7 -7 (same) -7 (same) -7 (same) -6 (slower) -7 (same)
Operating Temperature 0 °C to 85 °C (commercial extended) 0 °C to 85 °C (same) 0 °C to 85 °C (same) 0 °C to 85 °C (same) 0 °C to 85 °C (same) 0 °C to 85 °C (same)
Lifecycle Status Obsolete Obsolete Obsolete Obsolete Obsolete Obsolete

主な差別化要因

  • Higher logic density at same package （vs EP1S10B672C7N)
  • Drop-in density upgrade available （vs EP1S25F672C7N)
  • Lead-free variant exists in same package （vs EP1S20F672C7N)

設計ノート

The 672-BGA package measures 35 × 35 mm and typically exhibits theta-JA around 15-20 °C/W with forced airflow. Estimated: at 1.5 V core and 1.2 A core current (≈1.8 W core power) plus I/O bank dissipation, total device power can reach 4-7 W for typical designs. Add a heatsink or thermal pad for sustained high ambient temperatures.

Route 1.5 V core (VCCINT), PLL analog (VCCA_PLL), and I/O bank VCCIO supplies in separate power planes with star-ground returns. Use a 4-layer PCB at minimum with continuous power/ground planes directly beneath the BGA escape region. The 1.27 mm ball pitch requires laser-drilled or 4-mil mechanical micro-vias for inner-row escape to internal layers.

Stratix I requires a specific power-on sequence (VCCINT first, then VCCA_PLL, then VCCIO) - failure to follow this can trigger in-rush latch-up. Configure unused I/O pins as tri-stated inputs with weak pull-up in the Quartus II fitter settings. Configuration via passive serial (PS) mode requires a valid configuration clock on DCLK before CONF_DONE goes high.

The 672-BGA escape pattern uses dog-bone fanout to BGA pads on the top layer with micro-via transition to internal routing layers. Match-length tuning is required for LVDS pairs, SSTL memories, and clock-distribution nets to meet Stratix I timing closure at the -7 speed grade. Use the Quartus II TimeQuest timing analyzer with Synopsys Design Constraints (.sdc) files.

コンプライアンス情報

RoHS
Unknown
REACH
Unknown
AEC-Q100
Not Applicable
鉛フリー
Unknown
ハロゲンフリー
Unknown
紛争鉱物
Unknown

RoHS and lead-free status not explicitly stated in verified web data; the B (SnPb ball) suffix suggests a non-RoHS component, while F variants are lead-free. AEC-Q100 is not applicable for FPGAs. Always request manufacturer documentation for compliance verification on obsolete parts.

データ検証日: 2026-09-07 — データはXAIPARTの部品エンジニアリングチームによって検証・管理されています

関連検索

EP1S20B672C7N datasheet Altera Stratix EP1S20B672C7N EP1S20B672C7N price EP1S20B672C7N 672-BGA FPGA EP1S20B672C7N drop-in replacement Stratix 18460 logic elements FPGA EP1S20B672C7N vs EP1S25F672C7N EP1S20B672C7N obsolete alternative Stratix I ASIC prototyping FPGA EP1S20B672C7N buy online distributor what is the package of EP1S20B672C7N FPGA 672 BGA 426 IO 18k logic

関連部品&用語

Intel Altera EP1S20B672C7N Stratix Stratix I FPGA Field-Programmable Gate Array CMOS 0.13 µm process logic element LAB CLB TriMatrix memory block RAM DSP block BGA-672 672-BBGA 1.27 mm pitch RoHS JEDEC J-STD-020 Quartus II TimeQuest ASIC prototyping LVDS SSTL HSTL
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