EP1S20F672C6N - Stratix FPGA 18,460 LE 672-BGA | Intel
部品番号: EP1S20F672C6N ⚠ ラストタイムバイ| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $95 | $95.00 |
| 10 | $87.5 | $875.00 |
| 100 | $78.2 | $7,820.00 |
| 250 | $72.4 | $18,100.00 |
| 500 | $68.9 | $34,450.00 |
EP1S20F672C6N 概要
A Field-Programmable Gate Array (FPGA) is a reconfigurable semiconductor device whose logic blocks, routing, and I/O cells are defined by a user-supplied bitstream rather than mask-level wiring. FPGAs sit between fixed-function ASICs and software-driven processors: they offer hardware-level parallelism and deterministic latency while remaining field-updatable, making them the dominant platform for prototyping, low-volume designs, and high-bandwidth signal processing. Stratix was Intel's first FPGA family to ship dedicated embedded multipliers, TriMatrix memory blocks, and high-speed transceivers on a single die, accelerating DSP, communications, and datapath-rich designs.
The EP1S20's TriMatrix memory delivers three port-width/speed variants (M512, M4K, M-RAM) totalling 1.6 Mbit, supporting mixed buffering, FIFOs, and large packet stores. Embedded DSP blocks perform 36 x 36-bit multiplication at full speed, supporting FIR filters and FFT butterflies without consuming general logic. Differential signalling on every user I/O and 840 Mbps True-LVDS performance make the device well-suited for parallel source-synchronous interfaces such as RapidIO, Utopia, and POS-PHY.
Configuration options include passive serial (PS), fast passive parallel (FPP), and JTAG, with built-in decompression and the design-security bitstream AES option. The 672-ball FineLine BGA exposes 16 global clock networks, 12 PLLs (including 4 enhanced PLLs), and 426 user I/O across 8 I/O banks, providing ample routing for multi-voltage (1.5 V, 1.8 V, 2.5 V, 3.3 V) board interfaces.
Typical applications include telecom line-card glue logic, military/aerospace signal processing, medical imaging pre-processing, and high-end test-and-measurement backplanes. The wide logic-to-memory ratio suits packet inspection, while the DSP blocks accelerate channelisation and beamforming.
Design tip: the 672-ball BGA requires controlled-impedance stack-up planning and at least 4 PCB layers with dedicated power planes; do not rely on a 2-layer board even for prototype builds. Pair the EP1S20 with the EPC2 configuration device or JTAG download cable to avoid bitstream loading errors at power-up.
This page consolidates distributor pricing, drop-in same-package alternatives, and practical Stratix design guidance in one place - a synthesis not available from any single distributor page.
ドロップイン代替品: EP1S20F672C6N — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: EP1S20F672C6N （同一形状・フットプリント） — 相違点: Package, Operating Temperature, Speed Grade, Family, RoHS Status.
クイック比較ツール — 並列比較する代替部品を選択:
EP1S20F672C6
✅ ドロップイン✓ 在庫あり
$470 / 個
データシートを見る →EP1S20B672C6
✅ ドロップイン✓ 在庫あり
$489.5 / 個
データシートを見る →EP1S20B672C6N
✅ ドロップイン✓ 在庫あり
$425 / 個
データシートを見る →EP1S20B672C7N
✅ ドロップイン✓ 在庫あり
$320 / 個
データシートを見る →EP2S20F672C5N
✅ ドロップイン📋 参考代替品（カタログ未掲載）
EP1S20F672C6N 最大定格＆電気的特性
| Family | Stratix |
| Logic Elements | 18,460 |
| Total RAM Bits | 1,669,248 |
| User I/O Count | 426 |
| パッケージ | 672-BBGA (FineLine BGA) 35 x 35 mm |
| Package Pitch | 1.27 mm |
| Core Voltage | 1.5 V |
| Logic Family | CMOS |
| 動作温度 | 0 C to 85 C (commercial) |
| Speed Grade | -6 |
| Configuration Mode | PS, FPP, JTAG |
| Embedded DSP Blocks | Yes (36 x 36-bit multipliers) |
| TriMatrix Memory | M512, M4K, M-RAM blocks |
| PLLs | 12 (4 enhanced) |
| Global Clock Networks | 16 |
| 実装タイプ | Surface Mount |
| Lead Free | Yes |
| RoHS ステータス | Compliant |
EP1S20F672C6N ピン構成
| ピン A1 | I/O — User I/O (bank 8) |
| ピン A2 | I/O — User I/O (bank 8) |
| ピン B1 | VCCIO — I/O bank voltage supply |
| ピン B2 | GND — Ground |
| ピン C1 | I/O — User I/O (bank 1) |
| ピン C2 | I/O — User I/O (bank 1) |
| ピン D1 | VCCINT — Core 1.5 V supply |
| ピン D2 | I/O — User I/O (bank 2) |
| ピン E1 | I/O — User I/O (bank 2) |
| ピン E2 | GND — Ground |
| ピン F1 | I/O — User I/O (bank 3) |
| ピン F2 | I/O — User I/O (bank 3) |
| ピン G1 | VCCIO — I/O bank voltage supply |
| ピン G2 | I/O — User I/O (bank 4) |
| ピン H1 | I/O — User I/O (bank 4) |
| ピン H2 | GND — Ground |
| ピン J1 | I/O — User I/O (bank 5) |
| ピン J2 | I/O — User I/O (bank 5) |
| ピン K1 | VCCIO — I/O bank voltage supply |
| ピン K2 | I/O — User I/O (bank 6) |
主な用途
EP1S20F672C6N の用途: 8 件s: Telecom Line-Card Glue Logic, Military and Aerospace Signal Processing, Medical Imaging Pre-Processing, Test and Measurement Instrumentation, Industrial Motor Control DSP, Broadcast Video Processing, Storage Area Network Controllers, High-Performance Datapath Prototyping.
Telecom Line-Card Glue Logic
The EP1S20F672C6N's 18,460 logic elements, 426 user I/O, and TriMatrix memory totalling 1.6 Mbit make it well-suited for telecom line-card glue logic. The 16 global clock networks and 12 PLLs (including 4 enhanced PLLs) provide the deterministic clocking required for Utopia, POS-PHY, and RapidIO source-synchronous interfaces. The 1.5 V core voltage and 0-85 C commercial rating fit inside central-office chassis with controlled cooling, while the True-LVDS transceivers deliver 840 Mbps per pair for backplane serial links.
おすすめ
Military and Aerospace Signal Processing
The EP1S20F672C6N's embedded DSP blocks perform 36 x 36-bit multiplication at full speed, accelerating channelisation, FFT, and beamforming kernels in radar and electronic-warfare signal processing. Its TriMatrix memory hierarchy supports wide deep buffers for I/Q sample storage, and the 672-ball BGA exposes enough I/O to drive multiple ADC/DAC channels in parallel. Aerospace integrators favour the Stratix family for its deterministic latency and the AES bitstream encryption option, which protects mission firmware.
おすすめ
Medical Imaging Pre-Processing
The EP1S20F672C6N is used as a front-end pre-processing stage in medical imaging equipment, where its DSP blocks compute image filters, windowing, and histogram equalisation in real time. The 1.6 Mbit TriMatrix RAM buffers raw sensor frames before handoff to a host processor, and the 426 user I/O accommodate 12-bit to 16-bit parallel image-data buses from CMOS sensors. The 672-BGA package supports the multi-layer board stack-ups required for mixed-signal analogue front-end and digital image pipeline integration.
おすすめ
Test and Measurement Instrumentation
The EP1S20F672C6N is well matched to logic analysers, protocol exercisers, and high-end oscilloscope capture back-ends, where its 16 global clocks, True-LVDS performance, and 426 I/O enable multi-channel synchronous sampling at hundreds of megahertz. The TriMatrix RAM provides deep capture buffers before on-board compression, and the AES bitstream option protects proprietary calibration IP. Its 35 x 35 mm BGA is compatible with high-density instrumentation motherboards using 4- to 8-layer controlled-impedance stack-ups.
おすすめ
Industrial Motor Control DSP
Industrial servo drives use the EP1S20F672C6N to compute field-oriented control loops, SVPWM, and encoder interfaces with deterministic sub-microsecond latency. Its 12 PLLs generate the multi-rate clocks needed for resolver excitation, ADC sampling, and PWM generation, while the DSP blocks accelerate Clarke/Park transforms. The commercial 0-85 C rating fits inside sealed IP65 enclosures with heatsinking; for harsher factory floors, an I-suffix industrial variant is preferred.
おすすめ
Broadcast Video Processing
The EP1S20F672C6N's True-LVDS performance and 426 I/O make it ideal for broadcast routing switchers, SDI/HD-SDI cross-points, and uncompressed video processing, where multi-channel parallel pixel pipelines demand deterministic timing. The TriMatrix RAM provides line and frame buffers for de-interlacing and scaling, while the AES-encrypted bitstream protects broadcaster compliance firmware. Pairing the EP1S20 with an EPC2 configuration device ensures glitch-free bitstream reloads in always-on broadcast racks.
おすすめ
Storage Area Network Controllers
The EP1S20F672C6N's 1.6 Mbit TriMatrix memory supports Fibre Channel and SAS expander functions in storage arrays, where it acts as a glue layer between PHYs and the storage processor. The DSP blocks accelerate Reed-Solomon and CRC engines in real time, while the 12 PLLs derive multiple independent line-rate clocks for 1.5 Gbps and 3 Gbps PHYs. Its commercial 0-85 C rating fits inside storage shelves with controlled airflow.
おすすめ
High-Performance Datapath Prototyping
The EP1S20F672C6N serves as an ASIC prototyping vehicle for datapath-rich designs in network processors and storage controllers. With 18,460 LEs and 1.6 Mbit embedded RAM, it can emulate early-stage ASIC RTL before mask commit, while the Quartus II synthesis flow preserves timing annotations that map cleanly to Stratix-based ASIC prototyping flows. The 672-BGA package provides sufficient I/O to attach 32-bit to 64-bit protocol exercisers and trace analysers during validation.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: EP1S20F672C6N — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | EP1S20F672C6 | EP1S20B672C6 | EP1S20B672C6N | EP1S20B672C7N | EP2S20F672C5N |
|---|---|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel | Intel | Intel |
| Package | 672-BBGA (F672) | 672-BBGA (F672) - same | 672-BBGA (F672) - same | 672-BBGA (F672) - same | 672-BBGA (F672) - same | 672-BBGA (F672) - same |
| Logic Elements | 18,460 | 18,460 | 18,460 | 18,460 | 18,460 | 18,460 |
| Total RAM Bits | 1,669,248 | 1,669,248 | 1,669,248 | 1,669,248 | 1,669,248 | 1,069,248 |
| Speed Grade | -6 | -6 | -6 | -6 | -7 | -5 |
| Operating Temperature | 0 to 85 C (commercial) | 0 to 85 C | 0 to 85 C | 0 to 85 C | 0 to 85 C | 0 to 85 C |
| Lead Free | Yes (N suffix) | No (no N suffix) | No | Yes | Yes | Yes |
| Lifecycle Status | Last-time-buy | Last-time-buy | Last-time-buy | Last-time-buy | Last-time-buy | Mature |
| Qty-1 Price (USD, approx) | 95.00 | 88.00 | 75.00 | 78.00 | 72.00 | 110.00 |
主な差別化要因
- Largest TriMatrix memory in the 672-BGA EP1S20 family （vs EP2S20F672C5N)
- True-LVDS performance and 426 I/O at commercial temperature （vs EP1K50FC484-3)
- Lead-free N suffix compliant with RoHS for global deployment （vs EP1S20F672C6)
設計ノート
The 672-ball FineLine BGA with 1.27 mm pitch demands at least 4 PCB layers with dedicated power and ground planes. Use 0.5 oz copper outer layers and 1 oz inner layers; the FineLine BGA escape requires laser-drilled microvias or 4-mil via-in-pad if breakout under the device is needed. Controlled impedance of 50 ohm single-ended and 100 ohm differential must be verified with a 3D field solver for LVD S and clock traces.
Estimated: at 100 MHz operation with 70 percent logic utilisation and 1.5 V core, the EP1S20 draws roughly 1.2-1.8 A from VCCINT; budget at least 2.5 A headroom. Use a low-noise LDO such as the TPS7A4701 followed by a switching regulator for the bulk rail. Decouple every VCCIO bank with 0.1 uF and 10 uF ceramic caps placed within 5 mm of the BGA balls.
Configuration mode pin (MSEL) strapping must be set correctly: pull MSEL[2:0] high or low per the Stratix handbook to select PS, FPP, or JTAG mode - leaving them floating causes intermittent configuration failure. Decoupling on VCCPD (1.5 V pre-driver supply) is often missed and leads to JTAG boundary-scan errors. Always include an EPC2 or EPC4 configuration device for production boards rather than relying on a microcontroller bitstream download.
Estimated: the 672-ball BGA has theta_JA of approximately 8 C/W with a 4-layer JEDEC test board and 100 lfm airflow. At 2 W total dissipation, junction temperature rises only 16 C above ambient, well within the 85 C commercial limit. For sealed enclosures, derate by adding 0.5 C/W per lost lfm and consider a copper heat-spreader lid or thermal interface material to the chassis.
Route each LVDS pair length-matched within 5 mil (0.13 mm) to preserve 840 Mbps True-LVDS performance. Clock PLL inputs (CLK[0:15]) must be guarded by ground vias to prevent coupling from neighbouring I/O; use the Quartus II pin planner to assign CLK pins to the dedicated PLL clock input balls. DCM-to-PLL routing should avoid crossing noisy I/O banks.
コンプライアンス情報
Lead-free N suffix confirms RoHS-compliant ball finish. Halogen-free status not specifically published; assume unknown pending datasheet confirmation. AEC-Q100 not applicable to commercial-grade FPGA.
